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| document number: mc17XSF500 rev. 2.0, 9/2013 freescale semiconductor ? technical data * this document contains certain information on a new product. ? specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2013. all rights reserved. penta 17 mohm high side switch the 17XSF500 is the latest achievement in dc motor and lighting drivers. it belongs to an expandi ng family to control and diagnose various types of loads, such as in candescent lamps or light-emitting diodes (leds) with enhanced precision. it combines flexibility through daisy-chainable spi 5.0 mhz, extended digital and analog feedbacks, safety and robustness. output edge shaping helps to impr ove electromagnetic performance. to avoid shutting off the device upon inrush current, while still being able to closely track the load current, a dynamic overcurrent threshold profile is featured. current of each channel can be sensed with a programmable sensing ratio. whenever communication with the external microcontroller is lost, the device enters a fail operation mode, but remains operational, co ntrollable, and protected. this new generation of high side sw itch products family facilitates ecu design thanks to compatible mcu software and pcb foot print for each device variant. this family is packaged in a pb-free power-enhanced soic package with exposed pad which is end of li fe vehicles directive compliant. this device is powered by smartmos technology. features ? penta 17 m ? high side switches with hi gh transient current capability ? 16-bit 5.0 mhz spi control of overcurrent profiles, channel control including pwm duty cycles, output-on and -off openload detections, thermal shutdown and prewarning, and fault reporting ? output current monitoring with programmable synchronization signal and supply voltage feedback ? limp home mode ? external smart power switch control ? operating voltage is 7.0 to 18 v with sleep current < 5.0 a, extended mode from 6.0 to 28 v ?-16 v reverse polarity and ground disconnect protections ? compatible pcb foot print and spi software driver among the family figure 1. penta 17 mohm high side simplified application diagram enhanced penta high side switch 17XSF500 ek suffix (pb-free) 98asa00368d 32-pin soicw-ep applications ? low voltage exterior lighting ? low voltage industrial lighting ? low voltage automation systems ? halogen lamps ? incandescent bulbs ? light-emitting diodes (leds) ? hid xenon ballasts ? dc motors in4 vcc si csb so rstb clk csns limp in1 in2 in3 vpwr cp out1 out2 out3 out4 out5 out6 gnd out vpwr gnd csns smart power 17XSF500 vcc so csb sclk si rstb clk a/d1 trg1 a/d2 port port port port port gnd sclk syncb main mcu vcc vpwr gnd 5.0 v regulator v pwr v pwr in m solenoid led module dc motor resistive load bulb spare
analog integrated circuit device data ? 2 freescale semiconductor mc17XSF500 1 orderable parts this section describes the part numbers availa ble to be purchased along with their differences. valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to http:// www.freescale.com and perform a part number search for the following device number: 17XSF500. table 1. orderable part variations part number notes temperature (t a ) package out1 rds(on) out2 rds(on) out3 rds(on) out4 rds(on) out5 rds(on) out6 mc17XSF500ek (1) -40 to 125 c soic 32 pins exposed pad 17 m ? 17 m ? 17 m ? 17 m ? 17 m ? yes notes 1. to order parts in tape & real, add the r2 suffix to the part number. analog integrated circuit device data ? freescale semiconductor 3 mc17XSF500 table of contents 2 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 relationship between ratings and operating requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.5 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 general ic functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3.1 self-protected high side switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3.3 mcu interface and device control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.5.1 power off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.5.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.5.3 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5.4 fail mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5.5 mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.6 spi interface and configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6.2 spi input register and bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6.3 spi output register and bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.6.4 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.6.5 electrical characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 functional block requirements and behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 self-protected high side switches description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.2 output pulse shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.3 output protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1.4 output clamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1.5 digital diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.1.6 analog diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.2 power supply functional block description and application in formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.2.2 wake state reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.2.3 supply voltages disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3 communication interface and device control functional block description and application information . . . . . . . . . 55 6.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3.2 fail mode input (limp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3.3 mcu communication interface protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.4 external smart power control (out6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 analog integrated circuit device data ? 4 freescale semiconductor mc17XSF500 7 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.1.1 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.1.2 application instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.1.3 bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.2 emc & emi considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.2.1 emc/emi tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.2.2 fast transient pulse tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.3 robustness considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.4 pcb layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.5.1 thermal transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.5.2 r/c thermal model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.1 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.2 package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 analog integrated circuit device data ? freescale semiconductor 5 mc17XSF500 2 internal block diagram figure 2. simplifi ed internal block diagram (penta version) so vpwr gnd selectable slope control cp out1 selectable over- current protection temperature shut-down thermal prewarning selectable open- load detection output voltage monitoring selectable current sensing out1 channel spi pwm module fault management logic vcc csb sclk si rstb limp in1 in2 in3 in4 clk csns csns syncb out2 out3 out4 out5 selectable analog feedback control die temperature monitoring power voltage monitoring out6 v cc vpwr_protected vpwr_protected out2 channel out3 channel out4 channel out5 channel v cc reverse battery protection ovf otw1 otw2 ots1 oc1 olon1 oloff1 out1 clkf cpf charge pump spif vpwr_protected power supply out4 channel under-voltage detection uvf clock failure detection power-on reset v s selectable delay battery clamp spi control limp home control power channels smart power switch drive v cc a to d convertion v cc v pwr 100 nf 5k 5k reference pwm clock oscillator wakeb or rstb analog integrated circuit device data ? 6 freescale semiconductor mc17XSF500 3 pin connections 3.1 pinout diagram figure 3. 17XSF500 pinout diagram 3.2 pin definitions table 2. 17XSF500 pin definitions pin number pin name pin function formal name definition 1 cp internal supply charge pump this pin is the connection for an exter nal capacitor for charge pump use only. 2 rstb spi reset this input pin is used to initialize the device configuration and fault registers, as well as place the device in a lo w-current sleep mode. this pin has a passive internal pull-down. 3 csb spi chip select this input pin is connected to a chip select output of a master microcontroller (mcu). when this digital signal is hi gh, spi signals are ignored. asserting this pin low starts a spi transaction. the transaction is indicated as completed when this signal returns to a high level. this pin has a passive internal pull-up to v cc through a diode. 4 sclk spi serial clock this input pin is connected to the mcu providing the required bit shift clock for spi communication. this pin has a passive internal pull-down. 5 si spi serial input this pin is the data input of the spi communication interface. the data at the input is sampled on the positive edge of the sclk. this pin has a passive internal pull-down. 6 vcc power supply mcu power supply this pin is a power supply pin is for internal logic, the spi i/os, and the out6 driver. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 transparent top view cp rstb csb sclk si vcc so out6 gnd nc nc gnd out5 out5 out3 out3 out3 out1 out1 csns csns syncb in1 in2 in3 in4 limp clk vpwr out4 out4 out2 out2 out4 33 analog integrated circuit device data ? freescale semiconductor 7 mc17XSF500 7 so spi serial output this output pin is connected to the spi se rial data input pin of the mcu, or to the si pin of the next device of a dai sy chain of devices . the spi changes on the negative edge of sclk. when csb is high, this pin is high-impedance. 8 out6 output external solid state this output pin controls an external smar t power switch by logic level. this pin has a passive internal pull-down. 9, 24 gnd ground ground these pins are the ground for the logic and analog circuitries of the device. for esd and electrical parameter accu racy purpose, the ground pins must be shorted in the board. 10, 11 out2 output channel #2 protected high side power output pins to the load. 12, 13, 14 out4 output channel #4 protected high side power output pins to the load. 15, 16 nc n/a not connected these pins may not be connected. 17, 18 out5 output channel #5 protected high side power output pins to the load. 19, 20, 21 out3 output channel #3 protected high side power output pins to the load. 22, 23 out1 output channel #1 protected high side power output pins to the load. 25 csns feedback current sense this pin reports an analog value proportional to the designated out[1:5] output current, or the temperature of the exposed pad, or the supply voltage. it is used externally to generate a ground referenced voltage for the microcontroller (mcu). current recopy and analog voltage feedbacks are spi programmable. 26 csns syncb feedback current sense synchronization this open drain output pin allows syn chronizing the mcu a/d conversion. this pin requires an external pull-up resistor to v cc . 27 in1 input direct input #1 this input wakes up the device. this i nput pin is used to directly control corresponding channel in fail mode. during normal mode, the control of the outputs by the control inputs is spi programmable.this pin has a passive internal pull-down. 28 in2 input direct input #2 this input wakes up the device. this i nput pin is used to directly control corresponding channel in fail mode. during normal mode, the control of the outputs by the control inputs is spi programmable.this pin has a passive internal pull-down 29 in3 input direct input #3 this input wakes up the device. this i nput pin is used to directly control corresponding channel in fail mode. during normal mode, the control of the outputs by the control inputs is spi programmable.this pin has a passive internal pull-down 30 in4 input direct input #4 this input wakes up the device. this i nput pin is used to directly control corresponding channel in fail mode. du ring normal mode the control of the outputs by the control inputs is spi programmable.this pin has a passive internal pull-down 31 limp input limp home the fail mode can be activated by this digital input. this pin has a passive internal pull-down. 32 clk input/output device mode feedback reference pwm clock this pin is an input/output pin. it is used to report the device sleep-state information. it is also used to apply the reference pwm clock which will be divided by 2 8 in normal operating mode. this pin has a passive internal pull- down. 33 vpwr power supply supply power supply this exposed pad connects to the positive power supply and is the source of operational power for the device. table 2. 17XSF500 pin definitions(continued) pin number pin name pin function formal name definition analog integrated circuit device data ? 8 freescale semiconductor mc17XSF500 4 general product characteristics 4.1 relationship between ratings and operating requirements the analog portion of device is supplied by the voltage applied to the vpwr exposed pad. thereby the supply of internal circuit ry (logic in case of v cc disconnect, charge pump, gate drive, ...) is derived from the vpwr terminal. in case of reverse supply: ? the internal supply rail is protected (max. -16 v) ? the output drivers (out1? out5) are switched on to r educe the power consumption in the drivers, when using incandescent bulbs the device?s digital circuitry is powered by the voltage applied to the vcc pin. in case of a v cc disconnection, the logic part is supplied by the vpwr pin. the output driver for spi signals, clk pi n (wake feedback) and out6 are supplied by the vcc pin only. this pin shall be protected externally, in case of a reverse pola rity, or in case of high-voltage disturbance. figure 4. ratings vs. operating requirements (vpwr pin) figure 5. ratings vs. operating requirements (vcc pin) fatal range probable permanent failure reverse protection degraded operating range - reduced performance - full protection but accuracy not guaranteed - no pmw feature for uv to 6 v normal operating range full performance degraded operating range - reduced performance - full protection but accuracy not guaranteed potential failure - reduced performance - probable failure in case of short- circuit fatal range probable permanent failure u n de r v o l t a g e 7 . 0 v fatal range probable permanent failure accepted industry standard practices correct operation fatal range probable permanent failure - 1 6 v 4 0 v handling conditions (power off) 4 0 v 1 8 v - 1 6 v 5 . 5 v operating range 3 2 v fatal range probable permanent failure not operating range degraded operating range reduced performance normal operating range full performance degraded operating range reduced performance fatal range probable permanent failure v c c p o r 4 . 5 v operating range 7 . 0 v 5 . 5 v - 0 . 6 v ( 2 . 0 v t o 4 . 0 v ) analog integrated circuit device data ? freescale semiconductor 9 mc17XSF500 4.2 maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise noted. exceeding these ratings may caus e a malfunction or permanent damage to the device. symbol description (rating) min. max. unit notes electrical ratings v pwr vpwr voltage range -16 40 v v cc vcc logic supply voltage -0.3 7.0 v v in digital input voltage ? in1? in4 and limp ? clk, si, sclk, csb, and rstb -0.3 -0.3 40 20 v (2) v out digital output voltage ? so, csns, sync, out6, clk -0.3 20 v (2) i cl negative digital input clamp current ?5.0ma (3) i out power channel current ?5.5a (4) e cl power channel clamp energy capability ? initial t j = 25 c ? initial t j = 150 c ? ? 100 50 mj (5) v esd esd voltage ? human body model (hbm) - vpwr, power channel and gnd pins ? human body model (hbm) - all other pins ? charge device model (cdm) - corner pins ? charge device model (cdm) - all other pins -8000 -2000 -750 -500 +8000 +2000 +750 +500 v (6) notes 2. exceeding voltage limits on those pins may caus e a malfunction or permanent damage to the device. 3. maximum current in negative clamping for in1? in4, limp, rstb, clk, si, so, sclk, and csb pins 4. continuous high side output current rating so long as maximum junction temperature is not exceeded. calculation of maximum ou tput current using package thermal resistance is required. 5. active clamp energy using single-pulse method (l = 2.0 mh, r l = 0 ? , v pwr = 14 v). please refer to output clamps section. 6. esd testing is performed in accordance with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ? ), and the charge device model. analog integrated circuit device data ? 10 freescale semiconductor mc17XSF500 4.3 thermal characteristics 4.4 operating conditions this section describes the operating conditions of the device. conditions apply to all the following data, unless otherwise not ed. table 4. thermal ratings all voltages are with respect to ground unless otherwise noted. exceeding these ratings may caus e a malfunction or permanent damage to the device. symbol description (rating) min. max. unit notes thermal ratings t a t j operating temperature ? ambient ? junction -40 -40 +125 +150 c (7) t stg storage temperature -55 +150 c t pprt peak package reflow temperature during reflow ? 260 c (8) (9) thermal resistance and package dissipation ratings r ? jb junction-to-board ([1]soldered to board) ? 2.5 c/w (10) r ? ja junction-to-ambient, natural convection, four-layer board (2s2p) ? 19.4 c/w (11) (12) r ? jc junction-to-case (case top surface) ? 14.2 c/w (13) notes 7. to achieve high reliability over 10 y ears of continuous operation, the device's conti nuous operating junction temperature sho uld not exceed 125 ? ? c. 8. pin soldering temperature limit is for 10 seconds maximum duration. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 9. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics. 10. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 11. junction temperature is a function of di e size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 12. per jedec jesd51-6 with the board (jesd51-7) horizontal. 13. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1 ). table 5. operating conditions all voltages are with respect to ground unless otherwise noted. exceeding these ratings may caus e a malfunction or permanent damage to the device. symbol ratings min max unit notes v pwr functional operating supply voltage - device is fully functional. all features are operating. 7.0 18 v over voltage range ? jump start ? load dump ? ? 28 40 v reverse supply -16 ? v v cc functional operating supply voltage - device is fully functional. all features are operating. 4.5 5.5 v analog integrated circuit device data ? freescale semiconductor 11 mc17XSF500 4.5 supply currents this section describes the current cons umption characteristics of the device. table 6. supply currents characteristics noted under conditions 4.5 v ? v cc ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol ratings min typ. max unit notes vpwr current consumptions i qvpwr sleep mode measured at v pwr = 12 v ?t a = 25 c ?t a = 125 c ? ? 1.2 10 5.0 30 a (14) (15) i vpwr operating mode measured at v pwr = 18 v ?7.08.0ma (15) vcc current consumptions i qvcc sleep mode measured at v cc = 5.5v ? 0.05 5.0 a i vcc operating mode measured at v pwr = 5.5 v (spi frequency 5.0 mhz) ?2.84.0 ma notes 14. with the out1? out5 power channels grounded 15. with the out1? out5 power channels opened analog integrated circuit device data ? 12 freescale semiconductor mc17XSF500 5 general ic functional de scription and application information 5.1 introduction the 17XSF500 is an evolution of the successful gen3 by providin g improved features of a comp lete family of devices using freescale's latest and unique technologies for the controller and the power stages. it consists of a scalable family of device s compatible, in terms of software driver and package footprint. it allows diagnosing the light-emitting diodes (leds) with an enhanced cu rrent sense precision with synchronization pin, as well as driving high power motors with a perf ect control of its current consumption . it combines flexibility th rough daisy chainable spi 5.0 mhz, extended digital and analog feedbacks, safety, and robustness. it integr ates an enhanced pwm module with an 8-bit duty cycle capability and pwm frequency prescaler, per power channel. 5.2 features the main attributes of 17XSF500 are: ? penta high side switches wit h overload, overtemperature and undervoltage protection ? control output for one external smart power switch ? 16 bit spi communication interface with daisy chain capability ? integrated fail mode (asil b compliant functional safety behavior) ? dedicated control inputs for use in fail mode ? analog feedback pin with spi programmable multiplexer and sync signal ? channel diagnosis by spi communication ? advanced current sense mode for led usage ? synchronous pwm module with external clock, prescaler and multi-phase feature ? excellent emc behavior ? power net and reverse polarity protection ? ultra low power mode ? scalable and flexible family concept ? board layout compatible soic32 package with exposed pad analog integrated circuit device data ? freescale semiconductor 13 mc17XSF500 5.3 block diagram the choice of multi-die technology in soic exposed pad package including low cost vertical trench fet power die associated with smart power control die lead to an optimized solution. figure 6. functional block diagram 5.3.1 self-protected high side switches out1? out5 are the output pins of the power switches. the power channels are protected against various kinds of short- circuits and have active clamp circuitry that may be activated when switching off inductive loads. many protective and diagnost ic functions are available. 5.3.2 power supply the device operates with suppl y voltages from 5.5 to 40 v (v pwr ), but is full spec. compliant only between 7.0 and 18 v. the vpwr pin supplies power to the internal regulator, analog, and lo gic circuit blocks. the vcc pin (5.0 v typ.) supplies the outp ut register of the serial peripheral inte rface (spi). consequently, the spi regist ers cannot be read without presence of v cc . the employed ic architecture guarantees a low quiescent current in sleep mode. 5.3.3 mcu interface and device control in normal mode the power output channels are controlled by the embedded pwm module, which is c onfigured by the spi register settings. for bidirectional spi communication, v cc has to be in the authorized range. failure diagnostics and configuration are also performed through the spi port. the reported failure types are: open-load, short-circuit to supply, severe short-circuit t o ground, overcurrent, overtemperature, cl ock-fail, and under and overvoltage. the device allows driving loads at different frequencies up to 400 hz. 5.4 functional description the device has four fundamental operating mo des: sleep, normal, fail, and power off. it possesses multiple high side switches (power channels) each of which can be controlled independently: ? in normal mode by spi interface. for bidirecti onal spi communication, a second supply voltage (v cc ) is required. ? in fail mode by the corresponding the direct inputs in1? in4. the out5 for the penta version and the out6 are off in this mode. power supply gen4 - functional block diagram parallel control inputs mcu interface & device control spi interface self-protected supply mcu interface & output control self-protected high side switches pwm controller high side switches out[x] mcu interface analog integrated circuit device data ? 14 freescale semiconductor mc17XSF500 5.5 modes of operation the operating modes are based on the signals: ? wake = (in1_on) or (in2_on) or (in3_on) or (in4_on) or (rst\). more details in logic i/o plausibility check section. ? fail = (spi_fail) or (limp). more details in loss of communication interface section. figure 7. general ic operating modes 5.5.1 power off mode the power off mode is applied when v pwr and v cc are below the power on reset threshold (v pwr por , v cc por ). in power off, no functionality is av ailable but the device is protected by the clamping circuits. refer to the supply voltages disconnection section. 5.5.2 sleep mode the sleep mode is used to provide ultra low current consumption. during sleep mode: ? the component is inactive and all outputs are disabled ? the outputs are protected by the clamping circuits ? the pull-up / pull-down resistors are present the sleep mode is the default mode of the de vice after applying th e supply voltages (v pwr or v cc ) prior to any wake-up condition (wake = [0]). the wake-up from sleep mode is provided by the wake signal. wake = [0] wake = [0] wake = [1] fail = [1] fail = [0] and valid watchdog toggle fail normal sleep power off (v pwr < v pwrpor ) and (v cc < v ccpor ) (v pwr > v pwrpor ) or (v cc > v ccpor ) (v pwr < v pwrpor ) and (v cc < v ccpor ) (v pwr < v pwrpor ) and (v cc < v ccpor ) analog integrated circuit device data ? freescale semiconductor 15 mc17XSF500 5.5.3 normal mode the normal mode is the regular operating mode of the device. the device is in normal mode, when the device is in wake state (wake = [1]) and no fail condition (fail = [0]) is detected. during normal mode: ? the power outputs are under control of the spi ? the power outputs are controlled by the programmable pwm module ? the power outputs are protected by the overload protection circuit ? the control of the power outputs by spi programming ? the digital diagnostic feature transfers status of the smart switch via the spi ? the analog feedback output (csns and csns sync) can be controlled by the spi the channel control (chx) can be summarized: ? ch1? 4 controlled by onx or iinx (if ir is programmed by the spi) ? ch5? 6 controlled by onx ? rising chx by definition means starting overcurrent window for out1? 5. 5.5.4 fail mode the device enters the fail mode, when ? the limp input pin is high (logic [1]) ? or a spi failure is detected during fail mode (wake = [1] & fail = [1]): ? the out1? out4 outputs are directly controlle d by the corresponding control inputs (in1? in4) ? the out5? out6 are turned off ? the pwm module is not available ? while no spi control is feasible, the spi diagnosis is functional (depending on the fail mode condition): ? the so shall report the content of so register defined by soa0? 3 bits ? the outputs are fully protected in case of an overload, overtem perature and undervoltage ? no analog feedback is available ? the max. output overcurrent profile is activated (oclo and window times) ? in case of an overload condition or undervoltage, the auto-restart feature controls the out1? out4 outputs ? in case of an overtemperature condition or ochi1 detection or severe short-circuit detection, the corresponding output is latched off until a new wake-up event. the channel control (chx) can be summarized: ? ch1? 4 controlled by iinx, while the overcurrent windows are controlled by in_onx ? ch5? 6 are off 5.5.5 mode transitions after a wake-up: ? a power on reset is applied and all spi si and so registers are cleared (logic[0]) ? the faults are blanked during t blanking the device enters in normal mode after star t-up if following sequence is provided: ?v pwr and v cc power supplies must be above their undervoltage thresholds (sleep mode) ? generate wake-up event (wake=1) setting rstb from 0 to 1 the device initialization will be completed after 50 sec (typ). during this time, the device is robust, in case of v pwr interrupts higher than 150 nsec. the transition from ?normal mode? to ?fail mode? is executed immediately when a fail condition is detected. during the transition, the spi si settings are cleared and the spi so registers are not cleared. analog integrated circuit device data ? 16 freescale semiconductor mc17XSF500 when the fail mode condition was a: ? limp input, wd toggle timeout, wd t oggle sequence or a spi modulo 16 erro r, the spi diagnosis is available during fail mode ? si / so stuck to static le vel, the spi diagnosis is not available during fail mode the transition from ?fail mode? to ?normal mode? is enabled, when: ? the fail condition is removed and ? two spi commands are sent within a valid watchdog cycle (first wd = [0] and then wd = [1]) during this transition ? all spi si and so registers are cleared (logic[0]) ? the dsf (device status flag) in the registers #1? #7 a nd the rcf (register clearer flag) in the device status register #1 are set (logic[1]) to delatch the rcf diagnosis, a read command of the quick status register #1 must be performed. 5.6 spi interface and configurations 5.6.1 introduction the spi is used to ? control the device in case of normal mode ? provide diagnostics in case of normal and fail mode the spi is a 16-bit full-duplex synchronous data transfer interface with daisy chain capability. the interface consists of 4 i/o lines with 5.0 v cmos logic levels and termination resistors: ? the sclk pin clocks t he internal shift registers of the device ? the si pin accepts data into the input shift register on the rising edge of the sclk signal ? the so pin changes its state on the rising edge of sclk and reads out on the falling edge ? the csb enables the spi interface ? with the leading edge of csb the registers are loaded ? while csb is logic [0] si/so data are shifted ? with the trailing edge of the csb signal, spi da ta is latched into the internal registers ? when csb is logic [1], the signals at the sclk and si pins are ignored and so is high-impedance when the rstb input is ? low (logic [0]), the spi and the fault registers are reset. the wake state then depends on the status of the input pins (in_on1? in_on4) ? high (logic[1]), the device is in wake status and the spi is enabled the functionality of the spi is checked by a plausibility check. in case of a spi failure, the device enters the fail mode. 5.6.2 spi input register and bit descriptions the first nibble of the 16 bit data word (d15? d12) serves as address bits. 11 bits (d10? d1) are used as data bits. the d11 bit is the wd toggle bit. this bit has to be toggled with each write command. when the toggling of the bit is not executed wi thin the wd timeout, a spi fail is detected. all register values are logic [0] after a reset. the pr edefined value is off / inactive, unless otherwise noted. ? # d1 5 d 14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name wd si data 11 b i t d at a 4 bi t ad ress register si address analog integrated circuit device data ? freescale semiconductor 17 mc17XSF500 ? # d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 in i t ia li sa t io n 1 0 00 00wdwd sel sync en1 sync en0 mu x2 m ux1 mu x0 soa mod e soa3 soa2 soa1 soa0 in i t ia li sa t io n 2 1 00 01wd ochi thermal ochi tr a n sie n t no hid1 no hid0 ochi od5 ochi od4 ochi od3 ochi od2 ochi od1 pwm sync otw se l ch1 control 2 0 0 1 0 w d ph11 ph01 on1 pw m71 pwm61 pw m51 pwm41 pw m31 pwm21 pwm11 pw m01 ch2 control 3 0 0 1 1 w d ph12 ph02 on2 pw m72 pwm62 pw m52 pwm42 pw m32 pwm22 pwm12 pw m02 ch3 control 4 0 1 0 0 w d ph13 ph03 on3 pw m73 pwm63 pw m53 pwm43 pw m33 pwm23 pwm13 pw m03 ch4 control 5 0 1 0 1 w d ph14 ph04 on4 pw m74 pwm64 pw m54 pwm44 pw m34 pwm24 pwm14 pw m04 ch5 control 6 0 1 1 0 w d ph15 ph05 on5 pw m75 pwm65 pw m55 pwm45 pw m35 pwm25 pwm15 pw m05 ch6 control 7 0 1 1 1 w d ph16 ph06 on6 pw m76 pwm66 pw m56 pwm46 pw m36 pwm26 pwm16 pw m06 out put co n tr ol 8 1 0 0 0 w d p s f5 p sf 4 p s f3 ps f2 p s f1 on6 on5 on4 o n3 on2 on1 9-1 10 01wd0xxxx gpwm en6 gpwm en 5 gp w m en4 gpwm en3 gpwm en2 gpw m en1 9-2 10 01wd1xxgpwm7gpwm6gpwm5gpwm4gpwm3gpwm2gpwm1gpwm0 10-1 10 10wd0oclo5oclo4oclo3oclo2oclo1 acm en 5 acm en4 ac m en3 acm en2 acm en1 10-2 10 10wd1 no ochi5 no ochi4 no ochi3 no ochi2 no ochi 1 short ochi5 short ochi4 sh or t ochi3 short ochi2 sh or t ochi 1 input enable 11 1 0 1 1 w d 0 x x inen14 inen04 inen13 inen03 inen12 inen02 inen11 inen01 12-1 1 1 0 0 w d 0 prs15 prs05 prs14 prs04 prs13 prs03 prs12 prs02 prs11 prs01 12-2 1 1 0 0wd1 x xxx xx xxprs16prs06 ol control 13-1 11 01wd0 olon dgl5 olon dg l4 olon dgl3 olon dgl2 olon dgl1 oloff en 5 olo ff en4 oloff en3 olof f en2 oloff en1 olle d control 13-2 11 01wd1resresresres olle d tri g olle d en5 olled en4 olle d en3 olled en2 olled en 1 i n cr eme n t / dercrement 14 11 10wd in c r sg n incr15 incr05 incr14 incr04 incr13 incr03 incr12 incr02 incr11 incr01 te stmode 15 1 1 1 1 x xx xxx xx xx xx register si address si data global p wm co n tr ol o v er cu rr en t co ntr o l p re sca le r se ttings ? #0 ~# 14 = wa tch dog t og gle bi t #0 sync syn c sync sta tus #0 = a ddre ss of nex t so dat a word en1 en0 #0 = s ing le read a ddre ss of nex t so dat a wo rd 0 0 #0 = csns multiplexer setting 0 1 #0 = s ync d ela y set ti ng 1 0 #0 = wa tch dog t im eout sel ect 1 1 #1 = o ver t emp erat ure warn ing t hre sho ld sel ect ion #1 = r eset clo ck mo dule #1 no hid1no hid0 d selection #1 = o c h i windo w on l oad de man d 0 0 av aila ble f or all c han nels #1 = h i d out pu ts s elec ti on 0 1 av aila ble f or cha nne l 3 only #1 = o c h i1 le vel de pen din g o n con tro l die t emp erat ure 1 0 av aila ble f or cha nne ls 3 and 4 o nly #1 = o c h i1 le vel ad jus te d durin g o ff to o n t ra nsit io n 1 1 un ava ilab le fo r a ll ch anne ls #2~ #7 = p w m val ue (8bi t) #2~ #7 ph 1x ph 0x p ha se #2~ #7 = p has e con tro l 0 0 0 #2~ #8 = c han nel on /o ff inc l. o c hi c ont rol 0 1 90 #8 = p uls e skip pin g fea tu re fo r p ower out pu t ch anne ls 1 0 18 0 # 9-1 = g lob al pw m en abl e 1 1 27 0 # 9-2 = g lob al pw m va lue (8 bit ) #11 gpwm #10 -1 = a dva nce d curre nt s ense m ode e nab le enx outx pwmx outx pwmx #10 -1 = o c lo lev el co ntr ol 0 x x x o f f x of f x #10 -2 = u se sh ort o c hi wi ndo w t ime 0 o n individual on individual #10 -2 = s ta rt wit h o clo t hres hol d 1 o n gl obal on global #1 1 = i npu t en able c ont rol 0off individual on individual #1 2 = p re sca ler se tt ing 1off gl obal on global #13 -1 = o l l oad in o ff st at e enab le 0 o f f individual on individual #13 -1 = o l o n degl it ch ti me 1off gl obal on global #13 -2 = o l l ed mo de en able 0on individual on global #13 -2 = t rig ger f or o lled det et cio n in 100 % d. c. 1 o n gl obal on individual #1 4 = p w m inc reme nt / dec reme nt si gn #12 p rs 1x prs 0x pr s d i vi d er #1 4 = p w m inc reme nt / dec reme nt se tt in g 0 0 /4 2 5hz . .. . 10 0h z 0 1 /2 5 0hz . .. . 20 0h z #0 mu x2 mu x1 mu x0 csn s 1 x /1 1 00h z . .. . 4 00h z 000 #14 increment/decrement 001 010 011 #14 in c r 1x i nc r 0x i nc rem e nt/ d ecr em en t 1 0 0 0 0 no i ncrem ent / dec reme nt 101 01 110 1 0 111 1 1 vbat m oni to r 8 lsb con tro l die t emp erat ure 1 6 lsb o ut 2 cur rent 1 in crem ent o ut 3 cur rent o ut 4 cur rent o ut 5 cur rent 4 lsb of f incr sgn o ut 1 cur rent 0 de crem ent oll ed enx 11 oll ed trig incr sgn incr0x ~ incr1x inen0x ~ inen1x 01 p rs 0 x ~ pr s1 x olof f enx 10 olo n dglx ine n0x in x= 0 i nx= 1 acm enx oclox short ochix 1 00 no ochix onx ps fx gpwm enx gpwm 1 ~ g pwm 7 onx inen1x ochi odx no hidx ochi the rm al ochi t ra ns ient pwm 0x ~ pwm 7x ph0x ~ ph1x sync en0~ sync en1 trig0 wd sel trig1/2 otw se l pw m s y nc wd so a 0 ~ s oa 3 soa mode sy nc off mux0 ~ mux2 va lid vpwr monitor analog integrated circuit device data ? 18 freescale semiconductor mc17XSF500 5.6.3 spi output register and bit descriptions the first nibble of the 16 bit data word (d12? d15) serves as address bits. all register values are logic [0] after a reset, except dsf an d rcf bits. the predefined value is off / inactive unless otherwi se noted. qsfx #1 = quick s tatus (oc or otw or ots or olon or oloff) #2~#6 o c 2x o c1x o c 0x o ve r cu r re nt st atu s clkf #1 = pw m clo ck f ail f lag 0 0 0 n o ove rcu rrent rcf #1 = reg ist er c lea r f la g 0 0 1 o c h i1 cpf #1 = ch arge pum p fl ag 0 1 0 o c h i2 olf #1 ~# 7 = op en lo ad f lag (wi red or of all o l s ign als ) 0 1 1 o c h i3 ovlf #1 ~# 7 = ov er loa d fl ag (wire d or of all o c a nd o t s sig nal s) 1 0 0 o c lo dsf #1 ~# 7 = de vic e st at us f lag ( uvf or o vf or cp f or r cf or cl kf o r tm f ) 1 0 1 o c h io d fm #1 ~# 8 = f ail m ode f la g 110ssc oloffx #2 ~# 6 = op en lo ad in o ff st at e st at us b it 1 1 1 n ot u sed olonx #2 ~# 6 = op en lo ad in o n st at e st at us b it #9 devid2 devid1 devid0 device type otwx #2 ~# 6 = ov er te mp erat ur e wa rnin g bit 0 0 0 p ent a3 /2 ots x #2 ~# 6 = ov er te mp erat ur e shu td own bit 0 0 1 p ent a0 /5 il im p #7 = st at us o f li m p i npu t af t er de gli tc her (re port ed i n rea l t im e) 0 1 0 q u ad2 /2 spif #7 = spi fail flag 011quad0/4 uvf #7 = un der v olt ag e fla g 1 0 0 t rip le1 /2 ovf #7 = ov er vo lta ge f lag 1 0 1 t rip le0 /3 tmf #7 = t est mo de a ct iva ti on f lag 1 1 0 re s outx #8 = st at us o f vb at/ 2 c omp arat o r (re po rte d in rea l ti me) 1 1 1 re s iinx #8 = st at us o f i nx p in af t er de glit c her (re port ed i n real t im e) toggle #8 = st at us o f i nx _o n s ign als (i n 1_o n or i n2 _o n o r i n 3_o n or in 4_ o n) d evi d0 ~ de vid 2 #9 = de vic e ty pe d evi d3 ~ de vid 4 #9 = de vic e fa mil y d evi d5 ~ de vid 7 #9 = de sig n st at us (in cre men te d nu mbe r) status of vpwr/2 comparator (reported in real time) analog integrated circuit device data ? freescale semiconductor 19 mc17XSF500 5.6.4 timing diagrams figure 8. timing requirements during spi communication figure 9. timing diagram for serial output (so) data communication rstb csb sclk si don?t care must be valid don?t care v ih v il t wrst v ih v il v ih v il v ih v il must be valid t enbl 10% v cc 10% v cc t lead t wsclkh 90% v cc 10% v cc t rsi 90% v cc t cs t lag t fsi t wsclkl t si(su) t si(h) 90% v cc 10% v cc don?t care v ih v il so t soen tri-stated tri-stated t sodis sclk so v oh v ol t valid 90% v cc 10% v cc so high to low low to high v ol v ol v oh v oh t rsi t fsi 50% 10% v cc 90% v cc t rso t fso 10% v c analog integrated circuit device data ? 20 freescale semiconductor mc17XSF500 5.6.5 electrical characterization table 7. electrical characteristics characteristics noted under conditions 4.5 v ? v cc ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes spi signals cs\, si, so, sclk, so f spi spi clock frequency 0.5 ? 5.0 mhz v ih logic input high state level (si, sclk, csb, rstb) 3.5 ? ? v v ih(wake) logic input high state level for wake-up (rstb) 3.75 ? ? v v il logic input low state level (si, sclk, csb, rstb) ? ? 0.85 v v oh logic output high state level (so) vcc -0.4 ? ? v v ol logic output low state level (so) ??0.4v i in logic input leakage current in inactive state (si = sclk = rstb = [0] and csb = [1]) -0.5 ? +0.5 a i out logic output tri-state leakage current (so from 0 v to v cc ) -10 ? +1.0 a r pull logic input pull-up / pull-down resistor 25 ? 100 k ? c in logic input capacitance ? ? 20 pf (16) t rst_dgl rstb deglitch time 7.5 10 12.5 s t so so rising and falling edges with 80 pf ? ? 20 ns t wclkh required high state duration of sclk (required setup time) 80 ? ? ns notes 16. parameter is deri ved from simulations. spi signals cs\, si, so, sclk, so (continued) t wclkl required low state duration of sclk (required setup time) 80 ? ? ns t cs required duration from the rising to the falling edge of csb (required setup time) 1.0 ? ? s t rst required low state duration for reset rstb 1.0 ? ? s t lead falling edge of csb to rising edge of sclk (required setup time) 320 ? ? ns t lag falling edge of sclk to rising edge of csb (required setup lag time) 100 ? ? ns t si(su) si to falling edge of sclk (required setup time) 20 ? ? ns t si(h) falling edge of sclk to si (required hold time of the si signal) 20 ? ? ns t rsi si, csb, sclk, max. rise time allowing operation at maximum f spi ?2050ns t fsi si, csb, sclk, max. fall time allowing operation at maximum f spi ?2050ns t so(en) time from falling edge of csb to reach low-impedance on so (access time) ? ? 60 ns t so(dis) time from rising edge of csb to reach tri-state on so ? ? 60 ns analog integrated circuit device data ? freescale semiconductor 21 mc17XSF500 6 functional block requirements and behaviors 6.1 self-protected high side swit ches description and application information 6.1.1 features up to five power outputs are foreseen to drive light as well as dc motor applications. the outputs are optimized for driving bu lbs, but also hid ballasts, leds, and other resistive or low inductive loads. the smart switches are controlled by use of high sophisticated gate dr ivers. the gate drivers provide: ? output pulse shaping ? output protections ? active clamps ? output diagnostics 6.1.2 output pulse shaping the outputs are controlled with a closed loop active pulse shaping in order to provide the best compromise between: ? low switching losses ? low emc emission performance ? minimum propagation delay time depending on the programming of the prescaler setting register #12-1, #12-2 the switching speeds of the outputs are adjusted to the output frequency range of each channel. the edge shaping shall be designed according the following table: the edge shaping provides full symmetry for rising and falling transition: ? the slopes for the rising and falling edge are ma tched to provide best emc emission performance ? the shaping of the upper edges and the lower edges is matched to provide the best emc emission performance ? the propagation delay time for the ri sing edge and the fa lling edge are matched in order to provide true duty cycle control of the out put duty cycle error < 1 lsb at the max. frequency ? a digital regulation loop is used to mini mize the duty cycle erro r of the output signal ? divider factor min max min max min max min max 4 25 100 10 40 03 fb 4252 2 50 200 5 20 07 f7 8248 1 100 400 2, 5 1 0 07 f7 8248 pwm freq [hz] pwm peri od [m s] d. c. range [hex] d.c. range [lsb] 78 min. on/off duty cycle time [s] 15 6 15 6 analog integrated circuit device data ? 22 freescale semiconductor mc17XSF500 figure 10. typical power output switching (slow & fast slew rate) 6.1.2.1 spi control and configuration a synchronous clock module is integrated for optimized control of the outputs. the pwm frequency and output timing during normal mode is generated from the clock input (clk) by the inte grated pwm module. in case of clock fail (very low frequency, very high frequency), the output duty cycle is 100%. each output (out1? out6) can be controlled by an individual channel control register: where: ? ph0x? ph1x: phase assignment of the output channel x ? onx: on/off control including overcurrent window control of the output channel x ? pwm0x? pwm7x: 8-bit pwm value individually for each output channel x the onx bits are duplicated in the output control register #8, in order to control the outputs with either the chx control regi ster or the output co ntrol register. the prs1x? prs0x prescaler settings can be set in the prescaler settings register #12-1 and #12-2. the following changes of the duty cycle are perfo rmed asynchronous (with pos. edge of csb signal) ? turn on with 100% duty cycle (chx = on) ? change of duty cycle value to 100% ? turn off (chx = off) ? phase setting (ph0x? ph1x) ? prescaler setting (prs1x? prs0x) a change in phase setting or prescaler setting during chx = on may cause an unwanted long on -time. therefore it is recommended to turn off the output(s ) before execution of this change. ? # d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c h x co n tr ol 2~ 7 w d ph1x ph0x onx pw m7x pw m6x pw m5x pw m4x pw m3x pwm2x pwm1x pwm0x channel address register si addre ss si data analog integrated circuit device data ? freescale semiconductor 23 mc17XSF500 the following changes of the duty cycle are performed synchronous (with the next pwm cycle): ? turn on with le ss than 100% duty cycle (outx = onx) ? change of duty cycle value to less than 100% a change of the duty cycle value can be achieved by a change of the: ? pwm0x? pwm7x bits in individual channel control register #2? #7 ? gpwm en1? gpwm en6 bits (change between individual pwm and global pwm settings) in global pwm control register #9-1 ? incremental/decremental register #14 the synchronisation of the switching phases between different devi ces is provided by the pwm sync bit in the initialization 2 register #1. on a spi write into initialization 2 register (#1): ? initialization when the bit d1 (pwm sync) is logic[1], a ll counters of the pwm module are reset with the positive edge of csb, i.e. the phase synchroni zation is performed immediately within one spi frame. it could help to synchronize different gen4 devices in the board. ? when the bit d1 is logic[0], no action is executed the switching frequency can be adjusted for the corre sponding channel as described in the table below: no pwm feature is provided in case of: ?fail mode ? clock input signal failure ? div id er sl ew min. ma x. p rs1x prs0x fa ctor min ma x ra te [bit] [steps] 00 4 25 100 sl ow 01 2 50 200 sl ow 1x 1 100 4 00 fas t 25, 6 102,4 pwm fr eq [hz] 8 pwm resoluti on 256 clk fr eq. [khz] pre scale r se tting ? hex de c [ % ] s0 s1 s2 s3 s4 s5 s6 s7 ff 25 6 10 0 ,0 0 % ff f f ff f f ff ff ff ff fe 25 5 99,61% f7 f f ff f f ff ff ff ff fd 25 4 99,22% f7 f f ff f f f7 ff ff ff fc 25 3 98,83% f7 f f f7 f f f7 ff ff ff fb 25 2 98,44% f7 f f f7 f f f7 ff f 7 ff fa 25 1 98,05% f7 f 7 f7 f f f7 ff f 7 ff f9 25 0 97,66% f7 f 7 f7 f f f7 f7 f 7 ff f8 24 9 97,27% f7 f 7 f7 f7 f7 f7 f 7 ff f7 24 8 96,88% f6 24 7 96,48% f5 24 6 96,09% f4 24 5 95,70% .. . .. . .. . .. . 03 4 1,56% 02 3 1,17% 01 2 0,78% 00 1 0,39% pwm duty cycle pulse skipping frame ? incr sgn increment/decrement 0decrement 1 i ncre ment analog integrated circuit device data ? 24 freescale semiconductor mc17XSF500 6.1.2.2 global pwm control in addition to the individual pwm register, each chan nel can be assigned independently to a global pwm register. the setting is controlled by the gpwm en bits inside the global pwm control register #9-1. when no control by direct input pin is enabled and the gpwm en bit is ? low (logic[0]), the output is assigned to individual pwm (default status) ? high (logic[1]), the output is assigned to global pwm the pwm value of the global pwm channel is controlled by the global pwm control register #9-2. when a channel is assigned to global pwm, the switching phase the prescaler and the pulse skipping are according the corresponding output channel setting. 6.1.2.3 incremental pwm control to reduce the control overhead du ring soft start/stop of bulbs or dc motors (e.g . theatre dimming), an incremental pwm control feature is implemented. with the incremental pwm control feature, the pwm values of all internal channels out1? out5 can be incremented or decremented with one spi frame. the incremental pwm feature is not available for ? the global pwm channel ? the external channel out6 the control is according the increment/decrement register #14: ? incr sgn: sign of incremental dimming (valid for all channels) ? incr 1x, incr 0x increment/decrement this feature limits the duty cyc le to the rails (00 resp. ff) in order to avoid any overflow. 6.1.2.4 pulse skipping due to the output pulse shaping feature and the thereof resulting switch ing delay time of the smart switches, duty cycles close to 0% resp. 100% can not be generated by the device. therefore the pulse skipping feature (psf) is integrated to interpolate th is output duty cycle range in normal mode. the pulse skipping provides a fixed duty cycle pattern with 8 st ates to interpolate the duty cycle values between f7 (hex) and ff (hex). the range between 00 (hex) and 07 (hex) is not considered to be provided. the pulse skipping feature ? is available individually for the power output channels (out1? out5) ? is not available for the external channel (out6). ? gpwm enx chx pwmx chx pwmx 0 x x x of f x off x 0 o n individua l o n in divid ual 1on globa l on globa l 0 of f individua l o n in divid ual 1 of f globa l o n globa l 0 o n individua l o n globa l 1 o n globa l o n in divid ual 1 1 0 0 0 1 1 0 1 iinx=1 onx inen1x inen0x ii nx=0 ? incr 1x incr 0x incre ment/decreme nt 0 0 n o i ncrement/d ecre me nt 014 1 0 8 1 1 16 analog integrated circuit device data ? freescale semiconductor 25 mc17XSF500 the feature is enabled with the psf bits in the output control register #8. when the corresponding psf bit is ? low (logic[0]), the pulse skipping feature is disabled on this channel (default status) ? high (logic[1]), the pulse skipping feature is enabled on this channel 6.1.2.5 input control up to 4 dedicated control inputs (in1? in4) are foreseen to ? wake-up the device ? fully control the corresponding output in case of fail mode ? control the corresponding output in case of normal mode the control during normal mode is according the inen0x and inen1x bits in the input enable register #11. an input deglitcher is provided at each control input in order to avoid high frequency control of the outputs. the internal sig nal is called iinx. the channel control (chx) can be summarized: ? normal mode: ? ch1? 4 controlled by onx or inx (if it is programmed by the spi) ? ch5? 6 controlled by onx ? rising chx by definition means starting overcurrent window for out1? 5 ?fail mode: ? ch1? 4 controlled by iinx, while the over current windows are controlled by in_onx ? ch5? 6 are off the input thresholds are logic level compatible, so the input structure of the pins shall be able to withstand supply voltage l evel (max.40 v) without damage. external cu rrent limit resistors (i.e. 1.0 k...10 k) can be used to handle reverse current conditions. the inputs have an integrated pull-down resistor. 6.1.2.6 electrical characterization table 8. electrical characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes power outputs out1? out5 r ds(on) on-resistance, drain-to-source ?t j = 25 c, v pwr > 12 v ?t j = 150 c, v pwr > 12 v ?t j = 25 c, v pwr = 7.0 v ?t j = 25 c, v pwr = -12 v ?t j = 150 c, v pwr = -12 v ? ? ? ? ? 17 ? ? ? ? 19 30.9 25.5 31 43.5 m ? i leak sleep sleep mode output leakage current (output shorted to gnd) per channel ?t j = 25 c, v pwr = 12 v ?t j = 125 c, v pwr = 12 v ?t j = 25 c, v pwr = 35 v ?t j = 125 c, v pwr = 35 v ? ? ? ? ? ? ? ? 0.5 5.0 5.0 25 a i out off operational output leakage current in off-state per channel ?t j = 25c, v pwr = 18v ?t j = 125c, v pwr = 18v ? ? ? ? 10 20 a analog integrated circuit device data ? 26 freescale semiconductor mc17XSF500 6.1.3 output protections the power outputs are protected against fault c onditions in normal and fail mode in case of: ? overload conditions ? harness short-circuit ? overcurrent protection against ultra- low resistive short-circuit conditions due to smart over current profile & severe short-circuit protection ? overtemperature protection including overtemperature warning ? under and overvoltage protections ? charge pump monitoring ? reverse supply protection in case of a fault condition is detected, the corresponding output is directed to shut down immediately after the deglitch time t fault sd . the turn off in case of a fault shutdown (ochi1, ochi2, ochi3, oclo, ots, uv, cpf, oloff) is provided by the fto feature (fast turn off). the fto: ? does not use edge shaping ? is provided with high slew rate to minimize the output turn-off time t output sd , in regards to the detected fault ? uses a latch, which keeps the fto active during an undervoltage condition (0 < v pwr < v pwr uvf ) power outputs out1? out5 (continued) ? pwm output pwm duty cycle range (measured at v out = v pwr /2) ? low frequency range (25 to 100hz) ? medium frequency range (50 to 200hz) ? high frequency range (100 to 400hz) 4.0 8.0 8.0 ? ? ? 252 248 248 lsb sr rising and falling edges slew rate at v pwr = 14 v (measured from v out = 2.5 v to v pwr -2.5 v) ? low frequency range ? medium frequency range ? high frequency range 0.25 0.25 0.55 0.42 0.42 0.84 0.6 0.6 1.25 v/s (17) ? sr rising and falling edges sl ew rate matching at v pwr = 14 v (srr / srf) 0.9 1.0 1.1 (17) t dly turn-on and turn-off delay times at v pwr = 14 v ? low frequency range ? medium frequency range ? high frequency range 20 20 10 60 60 30 100 100 50 s (17) ? t dly turn-on and turn-off delay times matching at v pwr = 14 v ? low frequency range ? medium frequency range ? high frequency range -20 -20 -10 0.0 0.0 0.0 20 20 10 s (17) t output sd shutdown delay time in case of fault 0.5 2.5 4.5 s reference pwm clock f clk clock input frequency range 25.6 ? 102.4 khz notes 17. with nominal resistive load 5.0 ? . table 8. electrical characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes analog integrated circuit device data ? freescale semiconductor 27 mc17XSF500 figure 11. power output switching in nominal operation and in case of fault normal mode in case of a fault condition during normal mode: ? the status is reported in the quick status register #1 and the corresponding channel status register #2? #6. to restart the output ? the channel must be restarted by writing the corresponding on bit in the channel control register #2? #6 or output control register #8. analog integrated circuit device data ? 28 freescale semiconductor mc17XSF500 figure 12. output control diagram in normal mode ? [(set chx=1) & (fault x= 0)] or [(rewrite chx=1) & (t analog integrated circuit device data ? freescale semiconductor 29 mc17XSF500 fail mode in case of an overcurrent (ochi2, ochi 3, oclo) or undervoltage, the restart is controlled by the auto-restart feature figure 13. auto-restart in fail mode in case of an overtemperature (otsx), or severe short-circuit (sscx), or ochi1 ov ercurrent, the correspond ing output enters a latch off state until the nex t wake-up cycle or mode change figure 14. output control diagram in fail mode ? i oclo i threshold time i ochi3 i ochi2 t ochi2 t autorestart in case of succ ess ful autores tart (no fault_fail x event) oclo remains acti ve driver turned off in case of fault_fail x ( = oc or uv) event during autorestart driver turned on again with ochi2 after fault_fail x ( i nx _o n= 1 ) of f ochi1 ochi2 ochi3 (t > tochi1) auto restart remark: iinx:= external inputs in1~in4 after deglitcher sscx := severe short circuit detection oclo latch off (o tsx=1) or (ssc x=1) or (o chi1x=1) (uv =1) (inx_on=0) (t > tochi1+t ochi2) & (autorestart x=0) (t >toc hi 1+ tochi 2+ tochi 3) outx =off autorestart x=1 (uv=0) & (t > t autorestart) (t > tochi1+tochi2) & (autorestart=1) outx=i inx (uv =1) or (oclox=1) (uv =1) or (o chi3x =1) (uv =1) or (ochi2x=1) (inx_on=0) (inx_on=0) (inx_on=0) (inx_on=0) outx=iinx outx=iinx outx =iinx outx =off outx =off oc_fail x=0 autorestart x=0 (otsx=1) or (sscx=1) (o tsx=1) or (s scx=1) (otsx=1) or (s scx =1) definition of key logic signals: analog integrated circuit device data ? 30 freescale semiconductor mc17XSF500 6.1.3.1 overcurrent protections each output channel is protected agai nst overload conditions by use of a multilevel overcurrent shutdown. figure 15. transient over current profile the current thresholds and the threshold window times are fixed for each type of power channel. when the output is in pwm mode, th e clock for the ochi time counters (t ochi1 ? t ochi3 ) is gated (logic and) with the referring output control signal: ? the clock for the t ochi counter is activated when the output = [1] respectively chx = 1 ? the clock for the t ochi counter is stopped when the output = [0] respectively chx= 0 figure 16. transient overcurrent profile in pwm mode this strategy counts the ochi time only when the bulb is actually heated up. the wi ndow counting is stopped in case of uv, cpf and ots. a severe short-circuit protection (ssc) is implemented in order to limit the power dissipation in normal and fail modes, in cas e of a severe short-circuit event. this feature is active only for a very short period of time, during off-to-on transition. the load impedance is monitored during the output turn-on. ? current t oc hi 3 t o chi2 t oc hi 1 overcurrent threshold profile lamp current i ochi1 i ochi2 i ochi3 i oclo time cumulative t o chi3 current cumul ativ e t ochi2 cumulativ e t ochi1 i ochi1 i ochi2 i ochi3 i oclo analog integrated circuit device data ? freescale semiconductor 31 mc17XSF500 normal mode the enabling of the high current window (ochi 1? ochi3) is dependent on chx signal. when no control input pin is enabled, the control of the overcurrent window depends on the on bits inside channel control registers #2? #7 or the out put control register #8. when the corresponding chx signal is ? toggled (turn off and then on), the ochi window c ounter is reset and the full ochi windows are applied figure 17. resetable overcurrent profile ? rewritten (logic [1]), the ochi window time is proceeding without reset of the ochi counter figure 18. over current level fixed to oclo fail mode the enabling of the high current window (ochi1? ochi3) is dependent on inx_on toggle signal. the enabling of output (out1? 5) is dependent on chx signal. time i ochi1 i ochi2 i ochi3 i oclo current on bit =0 on bit =1 oclo fault detection overcurrent threshold profile channel current time i oclo current on bit =1 rewriting oclo fault detection analog integrated circuit device data ? 32 freescale semiconductor mc17XSF500 6.1.3.1.1 overcurrent control programming a set of overcurrent control programming functions is implemented to provide a flexible and robust system behavior: hid ballast profile (no_hid) a smart overcurrent window control strategy is implemented to tu rn on a hid ballast, even in case of a long power on reset time . when the output is in 100% pwm mode (including pwm clock failure in normal mode and iinx=1 in fail mode), the clock for the ochi2 time counter is divided by 8, when no l oad current is demanded from the output driver. ? the clock for the t ochi2 counter is divided by 8 when the openload signal is high (logic[1]), to accommodate the hid ballast being in power on reset mode ? the clock for the t ochi2 counter is connected directly to the window time counter when the openload signal is low (logic[0]), to accommodate the hi d demanding load current from the output figure 19. hid ballast overcurrent profile this feature extends the ochi2 time depending on the status of the hid ballast and ensures to bypass even a long power on reset time of hid ballast. nominal t ochi2 duration is up to 64 ms (instead of 8.0 ms). this feature is automatically active at the beginning of smart overcurrent window, except for ochi on demand as described below. the functionality is controlled by the no_hid1 and no _hid0 bits inside the initialization #2 register. when the no_hid1 and no_hid0 bits are respectively ? [0 0]: smart hid feature is available for all ch annels (default status and during fail mode) ? [0 1]: smart hid feature is available for channel 3 only ? [1 0]: smart hid feature is av ailable for channels 3 and 4 only ? [1 1]: smart hid feature is not available for any channel ochi on demand (ochi od) in some instances, a lamp might be unpowered when its supply is interrupted by the opening of a switch (as in a door), or by disconnecting the load (as in a trailer harness). in these cases, the driver should be tolerant of the inrush current that will occur when the load is reconnected. th e ochi on demand feature allows such control individually for each channel through the ochi odx bits inside the initialization #2 register. time i ochi1 i ochi2 i ochi3 i oclo current t ochi3 8 x t ochi2 t ochi1 overcurrent threshold profile channel current analog integrated circuit device data ? freescale semiconductor 33 mc17XSF500 when the ochi odx bit is: ? low (logic[0]), the channel operates in its normal, default mode. after end of ochi window timeout the output is protected with an oclo threshold. ? high (logic[1], the channel operates in the ochi on demand mode and uses th e ochi2 and ochi3 windows and times after an oclo event. to reset the ochi odx bit (logic[0]) and ch ange the response of the channel, first c hange the bit in the initialization #2 regi ster and then turn the channel off. the ochi odx bit is also reset after an overcurrent ev ent at the corresponding output. the fault detection status is r eported in the quick status regi ster #1 and the corresponding chan nel status registers #2? #6, a s presented in figure 20 . figure 20. ochi on demand profile oclo threshold setting the static overcurrent threshold can be prog rammed individually for each output in 2 levels in order to adapt low duty cycle dimming and a variety of loads. the csns recopy factor and oclo threshold depend on oclo and acm settings. the oclo setting is controlled by the oclox bits inside the overcurrent control register #10-1. when the oclox bit is ? low (logic[0]), the output is prot ected with the higher oclo threshold (default status and during fail mode) ? high (logic[1]), the lower oclo threshold is applied short ochi the length of the ochi windows can be short ened by a factor of 2, to accelerate the availability of the csns diagnosis, and to reduce the potential stress inside t he switch during an overload condition. the setting is controlled individually for each output by the short ochix bits insi de the overload control register #10-2. when the short ochix bit is ? low (logic[0]), the default ochi window times are applied (default status and during fail mode) ? high (logic[1]), the short ochi window times are applied (50% of the regular ochi window time) no ochi the switch on process of an output ca n be done without an ochi window, to accelerate the availability of the csns diagnosis. the setting is controlled individually for each channel by the no ochix bits inside the overcurrent control register #10-2. when the no ochix bit is ? low (logic[0]), the regular ochi window is ap plied (default status and during fail mode) ? high (logic[1]), the turn on of the output is provided without ochi windows the no ochi bit is applied in real time. the ochi window is left immediately when the no ochi is high (logic[1]). time t ochi3 current t ochi2 i ochi2 i ochi3 i oclo ochi2 fault reported ochi3 fault reported oclo fault reported ochi od fault reported solid line: nominal operation dotted lines: fault conditions analog integrated circuit device data ? 34 freescale semiconductor mc17XSF500 the overcurrent threshold i set to oclo when: ? the no ochix bit is set to logic [1] while chx is on or ? chx turns on if no ochix is already set thermal ochi to minimize the electro-thermal stress inside the device in case of short-circuit, the ochi1 level can be automatically adjuste d in regards to the control die temperature. the functionality is controlled for all channels by the ochi thermal bit inside the initialization 2. when the ochi thermal bit is: ? low (logic[0]), the output is pr otected with default ochi1 level ? high (logic[1]), the output is protec ted with the ochi1 level reduced by r thermal ochi = 15% (typ) when the control die temperature is above t thermal ochi = 63 c (typ) transient ochi to minimize the electro-thermal stress inside the device in case of short-circuit, the ochix le vels can be dynamically evaluate d during the off-to-on output transition. the functionality is controlled for all channels by the o chi transient bit inside the initialization 2 register. when the ochi transient bit is: ? low (logic[0]), the output is pr otected with default ochix levels ? high (logic[1]), the output is protected with an ochix levels d epending on the output voltage (v out ): ? ochix level reduced by r transient ochi = 50% typ for 0 < v out < v out detect (v pwr / 2 typ), ? default ochix level for v out detect < v out if the resistive load is less than v pwr /i ochi1 , the overcurrent threshold will be exceeded before output reaches v pwr / 2 and output current reaches i ochi1 . the output is then switched off at much lower and safer currents. when the load has significant series inductance, t he output current transition falls behind voltage with l load /r load constant time. the intermediate overcurrent threshol d could not reach and the output current continues to rise up to ochix levels. 6.1.3.1.2 electrical characterization table 9. electrical characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes power outputs out1? out5 i ochi1 high overcurrent level 1 ?t j = -40 c and 25 c ?t j = 150 c 42 40 48 46 54.4 54.4 a i ochi2 high overcurrent level 2 24.5 28.2 32.2 a i ochi3 high overcurrent level 3 14.8 17.3 19.5 a i oclo low overcurrent ? high level ? low level 8.8 4.4 10.8 5.3 13.2 6.6 a i oclo acm low overcurrent in acm mode ? high level ? low level 4.4 2.2 5.3 2.6 6.6 3.3 a r transient ochi high overcurrent ratio 1 0.45 0.5 0.55 r thermal ochi high overcurrent ratio 2 0.835 0.85 0.865 analog integrated circuit device data ? freescale semiconductor 35 mc17XSF500 6.1.3.2 overtemperature protection a dedicated temperature sensor is located on each power transistor, to protect the tr ansistors and provide spi status monitorin g. the protection is based on a two stage strategy. when the temperature at the sensor exceeds the: ? selectable overtemperature warning threshold (t otw1 , t otw2 ), the output stays on and the event is reported in the spi ? overtemperature threshold (t ots ), the output is switched off i mmediately after the deglitch time t fault sd and the event is reported in the spi after the deglitch time t fault sd . 6.1.3.2.1 overtemperat ure warning (otw) receiving a overtemperature warning: ? the output remains in current state ? the status is reported in the quick status register #1 and the corresponding channel status register #2? #6 the otw threshold can be selected by the otw sel bit inside the initialization 2 register #1. when the bit is ? low (logic[0]) the high overtemperature threshold is enabl ed (default status) ? high (logic[1]) the low overte mperature threshold is enabled to delatch the otw bit (otwx) ? the temperature has to drop below the corresponding overtemperature warning threshold ? a read command of the corresponding channel status register #2? #6 must be performed power outputs out1? out5 (continued) t thermal ochi temperature threshold for iochi1 level adjustment 50 63 70 c t ochi1 high overcurrent time 1 ? default value ? short ochi option 1.5 0.75 2.0 1.0 2.5 1.25 ms t ochi2 high overcurrent time 2 ? default value ? short ochi option 6.0 3.0 8.0 4.0 10 5.0 ms t ochi3 high overcurrent time 3 ? default value ? short ochi option 48 24 64 32 80 40 ms r sc min minimum severe short-circuit detection 10 ? ? m ? t fault sd fault deglitch time ? oclo and ochi od ? ochi1? 3 and ssc 1.0 1.0 2.0 2.0 3.0 3.0 s (18) t auto- restart fault auto-restart time in fail mode 48 64 80 ms t blanking fault blanking time after wake-up ? 50 100 s notes 18. guaranteed by testmode. table 9. electrical characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes analog integrated circuit device data ? 36 freescale semiconductor mc17XSF500 6.1.3.2.2 overtemperat ure shutdown (ots) during an over temperature shutdown: ? the corresponding output is disabled immediately after the deglitch time t fault sd . ? the status is reported after t fault sd in the quick status register #1 and the corresponding channel status register #2? #6. to restart the output after an overtemperature shutdown event in normal mode: ? the overtemperature condition must be removed, and the channel must be restarted with a write command of the on bit in the corresponding channel control register #2? #6, or in the output control register #8. to delatch the diagnosis: ? the overtemperature condition must be removed ? a read command of the corresponding channel status register #2? #6 must be performed to restart the output after an overtemperature shutdown event in fail mode ? a mode transition is needed. refer to the mode transitions section. 6.1.3.2.3 electrical characterization 6.1.3.3 undervoltage and overvoltage protections 6.1.3.3.1 undervoltage during an undervoltage condition (v pwrpor < v pwr < v pwr uvf ), all outputs (out1? out5) are switched off immediately after deglitch time t fault sd . the undervoltage condition is reported after the deglitch time t fault sd ? in the device status flag (dsf) in the registers #1? #7 ? in the undervoltage flag (uvf) insi de the device status register #7 normal mode the reactivation of the outputs is co ntrolled by the microcontroller. to restart the output the undervolt age condition must be removed and: ? a write command of the on bit in the corresponding ch annel control register #2? #6 or in the output control register #8 must be performed to delatch the diagnosis: ? the undervoltage condition must be removed ? a read command of the device status register #7 must be performed fail mode table 10. electrical characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes power outputs out1? out5 t ow overtemperature warning ?t ow1 level ?t ow2 level 100 120 115 135 130 150 c (19) t ots over temperature shutdown 155 170 185 c (19) t fault sd fault deglitch time ?ots 2.0 5.0 10 s notes 19. guaranteed by test mode. analog integrated circuit device data ? freescale semiconductor 37 mc17XSF500 when the device is in fail mode, t he restart of the outputs is cont rolled by the auto-restart feature. 6.1.3.3.2 overvoltage the device is protected against overvoltage on v pwr . during: ? jump start condition, the device may be oper ated, but with respect to the device limits ? load dump condition (v pwr ld max = 40 v) the device does not conduct energy to the loads the overvoltage condition (v pwr > v pwr ovf ) is reported in the: ? device status flag (dsf) in the registers #1? #7 ? overvoltage flag (ovf) inside the device status register #7 to delatch the diagnosis: ? the overvoltage condition must be removed ? a read command of the device status register #7 must be performed in case of an overvoltage (v pwr > v pwr high ), the device is not ?short-circuit? proof. 6.1.3.3.3 electrical characterization 6.1.3.4 charge pump protection the charge pump voltage is monitored to protect the smart switches in case of: ? power up ? failure of external capacitor ? failure of charge pump circuitry during power up, when the charge pump voltage has not yet sett led to its nominal output volt age range, the outputs cannot be turned on. any turn on command during this phase is ex ecuted immediately after settling of the charge pump. when the charge pump voltage is not within its nominal output voltage range: ? the power outputs are disabled immediately after the deglitch time t fault sd ? the failure status is reported after t fault sd in the device status flag dsf in the registers #1? #7 and the cpf in the quick status register #1 ? any turn on command during this phase is executed, including the ochi windows immediately after the charge pump output voltage has reached its valid range to delatch the diagnosis: ? the charge pump failure condition must be removed table 11. electrical characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes supply vpwr v pwr uvf supply undervoltage 5.0 5.25 5.5 v v pwr uvf hys supply undervoltage hysteresis 200 350 500 mv v pwr ovf supply overvoltage 28 30 32 v v pwr ovf hys supply overvoltage hysteresis 0.5 1.0 1.5 v v pwr ld max supply load dump voltage (2.0 min at 25 c) 40 ? ? v v pwr high maximum supply voltage for short-circuit protection 32 ? ? v t fault sd fault deglitch time ? uv and ov 2.0 3.5 5.5 s analog integrated circuit device data ? 38 freescale semiconductor mc17XSF500 ? a read command of the quick status register #1 is necessary 6.1.3.4.1 electrical characterization 6.1.3.5 reverse supply protection the device is protected agains t reverse polarity of the v pwr line. in reverse polarity condition: ? the output transistors out1? 5 are turned on to prevent the device from thermal overload ? the out6 pin is pulled down to gnd. an external current limit resistor shall be added in series with out6 terminal ? no output protection is available in this condition 6.1.4 output clamps 6.1.4.1 negative output clamp in case of an inductive load (l), the energy is dissipated after the turn-off inside the n-channel mosfet. when t cl (=io x l / v cl ) > 1.0 ms, the turn-off waveform can be simplified with a rectangle, as shown in figure 21 . figure 21. simplified negative output clamp waveform the energy dissipated in the n-channel mosfet is: e cl = 1/2 x l x io2 x (1+ v pwr / |v cl |). in the case of t cl < 1.0 ms, please contact the factory for guidance. table 12. electrical characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes charge pump cp c cp charge pump capacitor range (ceramic type x7r) 47 ? 220 nf v cp max maximum charge pump voltage ?? 16 v t fault sd fault deglitch time ?cpf ?4.0 6.0 s time output current io v bat v cl output voltage t cl time time v pwr v pwr analog integrated circuit device data ? freescale semiconductor 39 mc17XSF500 6.1.4.2 supply clamp the device is protected agains t dynamic overvoltage on the v pwr line by means of an active gate clamp, which activates the output transistors to limit the supply voltage (v dcclamp ). in case of an overload on an output, the corresponding switch is turned off, which leads to high voltage at v pwr with an inductive v pwr line. the maximum v pwr voltage is limited at v dcclamp by active clamp circuitry through the load. in case of an openload condition, the positive transient pulse s (acc.automotive specification iso 7637 / pulse 2 and inductive supply line) shall be handled by the applicati on. in case of negative transients on the v pwr line (acc. iso7637-2 / pulse 1), the energy of the pulses is dissipated inside the load, or shall be dr ained by an external clamping circuit, during a high ohmic lo ad. 6.1.4.3 electrical characterization 6.1.5 digital diagnostics the device offers several modes for load status detection in on state and off state through spi. 6.1.5.1 openload detections 6.1.5.1.1 openload in on state openload detection during on state is provided for each power output (out1? out5) based on the current monitoring circuit. the detection is activated automatically when the output is in on state. the detection threshold is dependent on: ? the olled en bits inside t he olled control register #13-2 the detection result is reported in: ? the corresponding qsfx bit in the quick status register #1 ? the global openload flag olf (registers #1? #7) ? the olon bit of the corresponding channel status registers #2? #6 to delatch the diagnosis ? the openload condition must be removed ? a read command of the corresponding channel status register #2? #6 must be performed when an openload has been detected, the output remains in on state. the deglitch time of the openload in on state can be controlled individually for each output in order to be compliant with diff erent load types. the setting is dependent on the olon dgl bits inside the openload control register #13-1: ? low (logic[0]) the deglitch time is t olon dgl = 64 s typ (bulb mode) ? high (logic[1]) the deglitch time is t olon dgl = 2.0 ms typ (converter mode) the deglitching filter is reset whene ver output falls low and is only active when the output is high. table 13. electrical characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes supply vpwr v dcclamp supply clamp voltage 41 ? 50 v power outputs out1? out5 v cl negative power channel clamp voltage -21 ? -18 v analog integrated circuit device data ? 40 freescale semiconductor mc17XSF500 6.1.5.1.2 openload in on state for led for detection of small load currents (e.g. le d) in on state of the switch a special lo w current detection mode is implemented b y using the olled en bit. the detection principle is based on a digital deci sion during regular switch off of the output. thereby a current source (i olled ) is switched on and the falling edge of the out put voltage is evaluated by a comparator at ? v pwr - 0.75 v (typ). . figure 22. openload in on st ate diagram for led the olled fault is reported when the output voltage is above v pwr - 0.75 v after 2.0 ms off-time, or at each turn-on command if the off-time < 2.0 ms. the detection mode is enabled individually for each channel wit h the olled en bits inside the led control register #13-2. when the corresponding olled en bit is ? low (logic[0]), the standard ope nload in on state (olon) is enabled ? high (logic[1]), the olled detection is enabled. the detection result is reported in: ? the corresponding qsfx bit in the quick status register #1 ? the global openload flag olf (register #1? #7) ? the olon bit of the corresponding channel status register #2? #6 when an openload has been detected, the output remains in on state. when output is in pwm operation: ? the detection is performed at the end of the on time of each pwm cycle ? the detection is active during the off time of the pwm signal, up to 2.0 ms max. the current source (i olled ) is disabled after ?no olled? detection or after 2.0 ms. v pwr v pwr analog integrated circuit device data ? freescale semiconductor 41 mc17XSF500 figure 23. openload in on state for led in pwm operation (off time > 2.0 ms) figure 24. openload in on state for led in pwm operation (off time < 2.0 ms) when output is in fully on operation (100% pwm): ? the detection on all outputs is triggered by setting th e olled trig bit inside the led control register #13-2 ? at the end of detection time, the current source (i olled ) is disabled 100 sec (typ.) after the output reactivation. en_olled_1 hson_1 128*dclock (prescaler = ?0?) v bat -0.75 out_1 out_high analog comparator output 0 : no olled detected 1 : olled detected check timeout = 2.0 msec vpwr -0.75 en_olled_1 hson_1 128*dclock (prescaler=?0?) v bat -0.75 out_1 out_high analog comparator output 0 : no olled detected 1 : olled detected check timeout = 2.0 msec vpwr -0.75 analog integrated circuit device data ? 42 freescale semiconductor mc17XSF500 figure 25. openload in on state for led in fully on operation the olled trig bit is reset after the detection. to delatch the diagnosis: ? a read command of the corresponding channel status register #2? #6 must be performed a false ?open? result could be reported in the olon bit: ? for high duty cycles, the pwm off-time becomes too short ? for capacitive load, the output voltage slope becomes too slow 6.1.5.1.3 openload in off state an openload in off state detection is provided individually for each power output (out1? out5). the detection is enabled individually for each channel by the oloff en bits inside the openload control register #13-1. when the corresponding oloff en is ? low (logic[0]), the diagnosis mo de is disabled (default status) ? high (logic[1]), the diagnosis mode is started for t oloff . it is not possible to restart any oloff or disable the diagnosis mode during active oloff state this detection can be activated independently for each power ou tput (out1? out5). but when it is activated, it is always activated synchronously for all selected outputs (with positive edge of cs\). when the detection is started, the corre sponding output channel is turned on wi th a fixed overcurrent threshold of i oloff threshold. when this over current threshold: ? is reached within the detection timeout t oloff , the output is turned off and t he oloff en bit is reset. no oclox and no oloffx will be reported ? is not reached within the detection timeout t oloff , the output is turned off after t oloff and the oloff en bit is reset. the oloffx will be reported the overcurrent behavior, as commanded by the overcurrent control settings (no ochix, ochi odx, shortochix, oclox, acm enx), is not be affected by applying the oloff enx bit. th e same is true for the output current feedback and the current sense synchronization. the detection result is reported: ? in the corresponding qsfx bit in the quick status register #1 ? in the global openload flag olf (register #1? #7) ? in the oloff bit of the corresponding channel status register #2? #6 olled trig 1 en_olled_1 hson_1 onoff & pwm ff timeout = 2.0 msec v bat -0.75 out_1 out_high analog comparator output 0 : no olled detected 1 : olled detected check check precision ~ 9600 ns note: olled trig bit is reset after the detection 100 ? sec 100 ? sec vpwr -0.75 analog integrated circuit device data ? freescale semiconductor 43 mc17XSF500 to delatch the diagnosis a read command of the correspo nding channel status register #2? #6 must be performed in case of any fault during t oloff (ots, uv, cpf,), the openload in off state de tection is disabled and the output(s) is (are) turned off after the deglitch time t fault sd . the corresponding fault is re ported in spi so registers. 6.1.5.1.4 electrical characterization 6.1.5.2 output shorted to vpwr in off state a short to v pwr detection during off state is provided individually fo r each power output out1? out5, based on an output voltage comparator referenced to v pwr / 2 (v out detect ) and external pull-down circuitry. the detection result is reported in the outx bits of the i/o status register #8 in real time. in case of uvf, the outx bits are undefined. 6.1.5.2.1 electrical characterization table 14. electrical characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes power outputs out1 ? out5 i ol openload current threshold in on state ?t j = -40 c ?t j = 25 c and 125 c 30 50 100 100 160 150 ma ? pwm olon output pwm duty cycle range for openload detection in on state ? low frequency range (25 to 100hz) ? medium frequency range (100 to 200hz) ? high frequency range (200 to 400hz) 18 18 17 ? ? ? ? ? ? lsb i olled openload current threshold in on state / olled mode 2.0 4.0 5.0 ma t olled100 maximum openload detection time / o lled mode with 100% duty cycle 1.5 2.0 2.6 ms t oloff openload detection time in off state 0.9 1.2 1.5 ms t fault sd fault deglitch time ?oloff ? olon with olon dgl = 0 ? olon with olon dgl = 1 2.0 48 1.5 3.3 64 2.0 5.0 80 2.5 s ms ms i oloff openload current threshold in off state 0.385 0.55 0.715 a table 15. electrical characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes power outputs out1 ? out5 v out detect output voltage comparator threshold 0.42 0.5 0.58 v pwr analog integrated circuit device data ? 44 freescale semiconductor mc17XSF500 6.1.5.3 spi fault reporting protection and monitoring of the output s during normal mode is provided by digital switch diagnosis via the spi. the selection of the so data word is controlled by the soa0? soa3 bits inside the initialization 1 register #0. the device provides two different reading modes, depending on the soa mode bit. when the soa mode bit is: ? low (logic[0]), the programmed so address will be used for a single read command. after the reading the so address returns to quick status register #1 (default state) ? high (logic[1]), the programmed so address will be used for the next and all further read commands until a new programming the ?quick status register? #1 provides one glance failure overvi ew. as long as no failure flag is set (logic[1]), no control a ction by the controller is necessary. ? fm: fail mode indication. this bit is present also in all other so data words and indicates the fail mode by a logic[1]. when the device is in normal mode, the bit is logic[0] ? global device status flags (d10? d8): these flags are al so present in the channel status registers #2? #6 and the device status register #7 and are cleared when all f ault bits are cleared by reading the registers #2? #7 ? dsf = device status flag (rcf, or uvf, or ovf, or cpf, or clkf, or tmf). uvf and tmf are also reported in the device status register #7 ? ovlf = overload flag (wired or of all oc and ots signals) ? olf = openload flag ? cpf: charge pump flag ? rcf: registers clear flag: this flag is set (l ogic[1]) when all si and so registers are reset ? clkf: clock fail flag. refer to logic i/o plausibility check section ? qsf1? qsf5: channel quick status flags (qsfx = oc0x, or oc1x, or oc2x, or otwx, or otsx, or olonx, or oloffx) the soa address #0 is also mapped to register #1 (d15? d12 bits will report logic [0001]). when a fault condition is indicated by one of the quick stat us bits (qsf1? qsf5, ovlf, olf), the detailed status can be evaluated by reading of the correspond ing channel status registers #2? #6. ? otsx: overtemperature shutdown flag ? otwx: overtemperature warning flag ? oc0x? oc2x: overcurrent status flags ? olonx: openload in on state flag ? oloffx: openload in off state flag the most recent oc fault is reported by the oc0x? oc2x bits if a new oc occurs before an old oc on the same output was read. when a fault condition is indicated by one of the global status bits (fm, dsf), the detailed st atus can be evaluated by reading of the device status registers #7. ? # d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 q u i ck s tatu s 1 0 0 0 1 fm ds f ov lf olf cp f rcf clk f q s f5 qs f4 qs f3 qs f2 qs f1 so data register so address ? # d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ch 1 statu s 2 0 0 1 0 f m dsf ovlf olf res ots1 otw1 oc21 oc11 oc01 olon1 oloff 1 ch 2 statu s 3 0 0 1 1 f m dsf ovlf olf res ots2 otw2 oc22 oc12 oc02 olon2 oloff 2 ch 3 statu s 4 0 1 0 0 f m dsf ovlf olf res ots3 otw3 oc23 oc13 oc03 olon3 oloff 3 ch 4 statu s 5 0 1 0 1 f m dsf ovlf olf res ots4 otw4 oc24 oc14 oc04 olon4 oloff 4 ch 5 statu s 6 0 1 1 0 f m dsf ovlf olf res ots5 otw5 oc25 oc15 oc05 olon5 oloff 5 so data register so address analog integrated circuit device data ? freescale semiconductor 45 mc17XSF500 ? tmf: test mode activation flag. test mode is used for manufac turing testing only. if this bit is set to logic [1], the mcu shall reset the device. ? ovf: overvoltage flag ? uvf: undervoltage flag ? spif: spi fail flag ? ilimp (real time reporting after the t in_dgl , not latched) the i/o status register #8 can be used for syste m test, fail mode test, and the power down procedure. the register provides the status of the control inputs, the t oggle signal and the power outputs st ate in real time (not latched ): ? toggle = status of the 4 input toggle signals (in1_on or in2_on or in3_on or in4_on), reported in real time ? iinx = status of iinx signal (real time reporting after the t in_dgl , not latched) ? outx = status of output pins outx (the detection threshold is v pwr /2) when an undervoltage condition does not occur the device can be clearly identified by the device id regist er #9 when the supply voltage is within its nominal range. the register delivers devidx bits = 41hex for the 17XSF500. during undervoltage condition (uvf =1), devidx bits report 00hex. ? # d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 device status 7 0111fmdsfovlfolfresresrestmfovfuvfspif ilimp so data register so addre ss ? # d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i/ o s tat us 8 1 0 0 0 f m re s tog gle iin4 iin3 iin2 iin1 out 5 out 4 out 3 out 2 out1 so da ta register so addres s ? # d15 d14 d1 3 d12 d11 d10 d9 d8 d 7 d 6 d5 d4 d3 d2 d1 d0 device id 9 1001xxxx devid 7 devi d 6 devid 5 devi d 4 devi d 3 devi d 2 devi d 1 devi d 0 reg ister so address so data analog integrated circuit device data ? 46 freescale semiconductor mc17XSF500 6.1.6 analog diagnostics the analog feedback circuit (csns) is implemented to provid e load and device diagnostics during normal mode. during fail and sleep modes the analog feedback is not available. the routing of the integrated multiplexe r is controlled by mux0? mux2 bits in side the initialization 1 register #0. 6.1.6.1 output current monitoring the current sense monitor provides a current proportional to the current of the selected outpu t (out1? out5). csns output delivers 1.0 ma full scale range current source r eporting channel 1? 5 current feedback (i fsr ). figure 26. output current sensing the feedback is suppressed during ochi window (t < t ochi1 + t ochi2 + t ochi3 ) and only enabled during low overcurrent shutdown threshold (oclo). during pwm operation the current feedback circuit (csns) de livers current only during the on time of the output switch. current sense settling time, t csns(set) , varies with current amplitude. current sense valid time, t csns(val) , depends on the pwm frequency. an advanced current sense mode (acm) is implemented in order to diagnose led loads in normal mode and to improve current sense accuracy for low current loads. in the acm mode, the offset sign of current sense amplifier is toggled on ev ery csns sync\ rising edge. the error amplifier offset contribution to the csns error can be fully eliminated from the measur ement result by averaging each two sequential current sense measurements. the acm mode is enabled with the acm enx bits inside the acm control register #10-1. when the acm enx bit is: ? low (logic[0]), acm disabled (default status and during fail mode) ? high (logic[1]), acm enabled in acm mode: ? the precision of the current recopy feature (csns) is improved especially at lo w output current by averaging csns reporting on sequential pwm periods ? the current sense full scale range (fsr) is reduced by a factor of two ? the overcurrent protection threshold oc lo is reduced by a factor of two the following figure describes the timings between the selected channel current and the analog fe edback current. current sense validation time pertains to stabilization ti me needed after turn on. current sense settling time pertains to the stabilization time needed after the load current changes while the output is continuously on, or when anot her output signal is selected. 1.0 ma 0 ma i csns / i out = 1.0 ma / (100% fsr) typ note: fsr value depends on spi setting i csns 100% fsr 1% fsr i out ? #2~ #6 oc2x oc1x oc0x over current status 0 0 0 n o ov erc urre nt 001ochi1 010ochi2 011ochi3 100oclo 101ochiod 110ssc 1 1 1 n ot us ed analog integrated circuit device data ? freescale semiconductor 47 mc17XSF500 figure 27. current sensing response time internal circuitry limits the voltage of th e csns pin when its sense resistor is abs ent. this feature prevents damage to other circuitry sharing that electrical node; such as a microcontroller pin. several 17XSF500 may be connected to one shared csns resistor. 6.1.6.2 supply voltage monitoring the v pwr monitor provides a voltage proportional to the supp ly tab. the csns voltage is proportional to the v pwr voltage as shown. figure 28. supply voltage reporting hsonx time time time csns i outx t dly(on) t dly(off) t csns(set) t csns(val) +/- 5% of new value 5.0 v 0 v v pwrpor 20 v v csns / v pwr = ? typ v csns v pwr analog integrated circuit device data ? 48 freescale semiconductor mc17XSF500 6.1.6.3 temperature monitoring the average temperature of the control die is monitored by an analog temperature se nsor. the csns pin can report the voltage of this sensor. the chip temperature monitor output voltage is independent of the resistor connected to the csns pin, provided the resistor is within the min/max range of 5.0 k ? to 50 k ? . temperature feedback range, t fb , -40 c to 150 c. figure 29. temperature reporting 6.1.6.4 analog diagnostic synchronization a current sense synchronization pin is provided to si mplify the synchronous sampling of the csns signal. the csns sync\ pin is an open drain requiring an external 5.0 k ? (min) pull-up resistor to v cc . the csns sync signal is: ? available during normal mode only ? behavior depends on the type of signal selected by the mu x2? mux0 bits in the initialization 1 register #0. this signal is either a current proportional to an output current or a voltage propor tional to temperature or the supply voltage. current sense signal when a current sense signal is selected: ? the pin delivers a recopy of the output control signal during on phase of the pwm defined by the sync en0, sync en1 bits inside the initialization 1 register #0. v csns t j -40c 150c v fb 25c v csns / t j = v fbs analog integrated circuit device data ? freescale semiconductor 49 mc17XSF500 figure 30. csns sync\ valid setting figure 31. csns sync\ trig0 setting out1 time out2 time out1 for csns selected out2 for csns selected change of csns mux from out1 to out2 time csns sync\ active (low) csns sync\ csns sync\ blanked t dly(on) +t csns(set) out1 time out2 time out1 for csns selected out2 for csns selected time change of csns mux from out1 to out2 csns sync\ csns sync\ blanked until rising edge of the 1 st complete pwm cycle analog integrated circuit device data ? 50 freescale semiconductor mc17XSF500 figure 32. csns sync\ trig1/2 setting ? the csns sync\ pulse is suppressed duri ng ochi and during off phase of the pwm ? the csns sync\ is blanked during settling time of the csns multiplexer and acm switching by a fixed time of t dly(on) + t csns(set) ? when a pwm clock fail is de tected, the csns sync\ delivers a signal with 50% duty cycle at a fixed period of 6.5 ms ? when the output is programmed with 100% pwm, the csns sy nc\ delivers a logic[0] a high pulse with the length of 100 s typ during the pwm counter overflow fo r trig0 and trig1/2 settings, as shown in figure 33 figure 33. csns sync\ when the output is programmed with 100% out1 time out2 time out1 for csns selected out2 for csns selected time change of csns mux csns sync\ active (low) from out1 to out2 csns sync\ csns sync\ blanked until 1 rst valid edge generated in the middle of the out2 pulse out1 time out2 time out1 for csns selected out2 for csns selected time change of csns mux from out1 to out2 csns sync\ t dly(on) +t csns(set) analog integrated circuit device data ? freescale semiconductor 51 mc17XSF500 ? during an output fault, the csns sync\ signal for current sensing does not deliver a trigger signal until the output is enabled again. temperature signal or v pwr monitor signal. when a voltage signal (average control die temperature or supply voltage) is selected: ? the csns sync\ delivers a signal with 50% duty cycle and the period of the lowest pr escaler setting ? (f clk / 1024) ? and a pwm clock fail is detected, the csns sync\ deliv ers a signal with 50% duty cycle at a fixed period of 6.5ms (t sync default ). 6.1.6.5 electrical characterization table 16. electrical characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes current sense csns r csns current sense resistor range 5.0 ? 50 k ? i csns leak current sense leakage current when csns is disabled -1.0 ? +1.0 a v cs current sense clamp voltage 6.0 ? 8.0 v i fsr current sense full scale range ? high oclo and acm = 0 ? low oclo and acm = 0 ? high oclo and acm = 1 ? low oclo and acm = 1 ? ? ? ? 11 5.5 5.5 2.75 ? ? ? ? a acc i csns current sense accuracy for 9.0 v < v pwr < 18 v ?i out = 80% fsr ?i out = 25% fsr ?i out = 10% fsr with acm = 0 ?i out = 10% fsr with acm = 1 ?out1, out2 and out5 ?out3 and out4 ?i out = 5.0% fsr with acm = 0 ?i out = 5.0% fsr with acm = 1 ?out1, out2, and out5 ?out3 and out4 -11 -14 -20 -20 -25 -29 -29 -40 ? ? ? ? ? ? ? ? +11 +14 +20 +20 +25 +29 +29 +40 % (20) acc i csns 1 cal 2% current sense accuracy for 9.0 v < v pwr < 18 v with 1 calibration point at 25 c for 2.0% fsr and v pwr = 14 v ?i out = 80% fsr ?i out = 25% fsr ?i out = 10% fsr ?i out = 5.0% fsr -7.0 -7.0 -20 -29 ? ? ? ? +7.0 +7.0 +20 +29 % (20) (22) acc i csns 1 cal 50% current sense accuracy for 9.0 v < v pwr < 18 v with 1 calibration point at 25 c for 50% fsr and v pwr = 14 v ?i out = 80% fsr ?i out = 20% fsr ?i out = 15% fsr ?i out = 10% fsr ?i out = 5.0% fsr -7.0 -7.0 -10 -20 -35 ? ? ? ? ? +7.0 +7.0 +10 +20 +35 % (20) (22) analog integrated circuit device data ? 52 freescale semiconductor mc17XSF500 current sense csns (continued) acc i csns 2 cal current sense accuracy for 9.0 v < v pwr < 18 v with 2 calibration points at 25 c for 2.0% and 50% fsr and v pwr = 14 v ?i out = 80% fsr ?i out = 25% fsr ?i out = 10% fsr ?i out = 5.0% fsr ? out1 and out2 ? out3, out4, and out5 -6.0 -6.0 -8.0 -11 -21 ? ? ? ? ? +6.0 +6.0 +8.0 +11 +21 % (20) (22) i csnsmin minimum current sense reporting ?for 9.0 v < v pwr < 18 v ? out1 and out2 ? out3, out4, and out5 ? ? ? ? 1.0 2.0 % (20) (23) v pwr supply voltage feedback range v pwrma x ?20v acc v pwr supply feedback precision ? default ? 1 calibration point at 25 c and v pwr = 12 v, for 7.0 v < v pwr < 20 v ? 1 calibration point at 25 c and v pwr = 12 v, for 6.0 v < v pwr < 7.0 v -5.0 -1.0 -2.2 ? ? ? +5.0 +1.0 +2.2 % (22) t fb temperature feedback range -40 ? 150 c (21) v fb temperature feedback voltage at 25 c ?2.31 ? v coef v fb temperature feedback thermal coefficient ? 7.72 ? mv/c (22) acc ? t fb temperature feedback voltage precision ? default ? 1 calibration point at 25 c and v pwr = 7.0 v -15 -5.0 ? ? +15 +5.0 c (22) t csns(set) current sense settling time ? current sensing feedback for i out from 75% fsr to 50% fsr ? current sensing feedback for i out from 10% fsr to 1.0% fsr temperature and supply voltage feedbacks ? ? ? ? ? ? 40 260 10 s (21) t csns(val) current sense valid time current sensing feedback ? low / medium frequency ranges for i out > 20% fsr ? low / medium frequency ranges for i out < 20% fsr ? high frequency range for i out > 20% fsr ? high frequency range for i out < 20% fsr temperature feedback supply voltage feedback 10 70 5.0 70 ? ? ? ? ? ? ? ? 150 300 75 300 10 15 s (24) t sync default current sense synchronization period for pwm clock failure 4.8 6.5 8.2 ms table 16. electrica l characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes analog integrated circuit device data ? freescale semiconductor 53 mc17XSF500 6.2 power supply functional bl ock description and application information 6.2.1 introduction the device is functional when wake = [1 ] with supply voltages from 5.5 to 40 v (v pwr ), but is fully specification compliant only between 7.0 and 18 v. the vpwr pin supplies power to the internal re gulator, analog, and logic circuit blocks. the v cc pin (5.0 v typ.) supplies the output regi ster of the serial peripheral interface (spi) and the out6 driver. consequently, the spi regist ers cannot be read without presence of v cc . the employed ic architecture guarantees a low quiescent current in sleep mode (wake= [0]). 6.2.2 wake state reporting the clk input/output pin is also used to report the wake state of the device to the microcontroller as long as rstb is logic [0 ]. when the device is in: ? ?wake state? and rstb is inactive, t he clk pin reports a high signal (logic[1]) ? ?sleep mode? or the device is wake by the rstb pin, the clk is an input pin 6.2.2.1 electrical characterization current sense synchronization csns sync\ r csns sync pull-up current sense synchronization resistor range 5.0 ? ? k ? v ol current sense synchroni zation logic output low state level at 1.0 ma ?? 0.4v i out max current sense synchronization leakage current in tri-state (csns sync from 0 v to 5.5 v) -1.0 ? +1.0 a notes 20. precision either oclo and acm setting. 21. parameter is derived mainly from simulations. 22. parameter is guaranteed by design charac terization. measurements are taken from a st atistically relevant sample size across process variations. 23. error of ? 100% without calibration and ? 50% with 1 calibration point done at 25 c. 24. tested at 5% of final value at v pwr = 14 v, current step from 0 a to 2.8 a (or 5.6 a). parameter guaranteed by des ign at 1% of final value. table 17. electrical characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes clock input/output clk v oh logic output high state level (clk) at 1.0 ma v cc - 0.6 ? ? v table 16. electrica l characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes analog integrated circuit device data ? 54 freescale semiconductor mc17XSF500 6.2.3 supply voltages disconnection 6.2.3.1 loss of v pwr in case of a v pwr disconnection (v pwr < v pwr por ), the device behavior depends on the v cc voltage value: ?v cc < v cc por : the device enters the power off mode. all outputs are shut off immediately. all registers and faults are cleared. ?v cc > v cc por : all registers and faults are maintained. out1? 5 are shut off immediatel y. the on/off state of out6 depends on the current spi configur ation. spi reporting is available when v cc remains within its operating voltage range (4.5 to 5.5 v). the wake-up event is not reported to clk terminal. the clamping structures (supply cl amp, negative output clamp) are available to protect the device. no current is conducted from v cc to v pwr . an external current path shall be available to drain the energy from an inductive load in case of supply disconnection occurs w hen an output is on. 6.2.3.2 loss of v cc in case of v cc disconnection the device behavior depends on v pwr voltage: ?v pwr < v pwr por : the device enters the power off mode. all output s are shut off immediately. all registers and faults are cleared. ?v pwr > v pwr por : the spi is not available. therefor e, the device will enter wd timeout. the clamping structures (supply cl amp, negative output clamp) are available to protect the device. no current is conducted from v pwr to v cc . 6.2.3.3 loss of device gnd during loss of ground, the device cannot drive the loads, t herefore the out1? out5 outputs are switched off and the out6 voltage is pulled up. the device shall not be damaged by this failure condition. for protection of the digital inputs series resistors (1.0 k ? typ) can be provided externally in order to limit the current to i cl . 6.2.3.4 electrical characterization table 18. electrical characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes supply vpwr v pwr por supply power on reset 2.0 3.0 4.0 v vcc v cc por vcc power on reset 2.0 3.0 4.0 v ground gnd v gnd shift maximum ground shift between gnd pin and load grounds -1.5 ? +1.5 v analog integrated circuit device data ? freescale semiconductor 55 mc17XSF500 6.3 communication interface and d evice control functional block description and application information 6.3.1 introduction in normal mode the power output channels are controlled by the embedded pwm module, which is c onfigured by the spi register settings. for bidirectional spi communication, v cc has to be in the authorized range. failure diagnostics and configuration are also performed through the spi port. the reported failure types ar e: openload, short-circuit to supply, severe short-circuit to ground, overcurrent, overtemperature, clock fail, and under and overvoltage. for direct input control, the device shall be in fail-safe mode. v cc is not required and this mode can be forced by limp input pin. 6.3.2 fail mode input (limp) the fail mode of the component can be activated by limp direct input. the fail mode is activated when the input is logic [1]. in fail mode, the channel power outputs ar e controlled by the corresponding inputs. ev en though the input thresholds are logic level compatible, the input structur e of the pins shall be able to withstand supply voltage level (max. 40 v) without damage. external current limit resistors (i.e. 1.0 k ? ...10 k ? ) can be used to handle reverse current conditions. the direct inputs have an integrated pull-down resistor. the limp input has an integrated pull-down resistor. the status of the limp input can be monitored by the limp in bit inside th e device status register #7. 6.3.2.1 electrical characterization table 19. electrical characteristics characteristics noted under conditions 4.5 v ? v pwr ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes fail mode input limp v ih logic input high state level 3.5 ? ? v v il logic input low state level ??1.5v i in logic input leakage current in inactive state (limp = [0]) -0.5 ? +0.5 a r pull logic input pull-down resistor 25 ? 100 k ? c in logic input capacitance ? ? 20 pf (25) direct inputs in1? in4 v ih logic input high state level 3.5 ? ? v v ih(wake) logic input high state level for wake-up 3.75 ? ? v v il logic input low state level ??1.5v i in logic input leakage current in inactive state (forced to [0]) -0.5 ? +0.5 a r pull logic input pull-down resistor 25 ? 100 k ? c in logic input capacitance ? ? 20 pf (25) notes 25. parameter is derived mainly from simulations. analog integrated circuit device data ? 56 freescale semiconductor mc17XSF500 6.3.3 mcu communication interface protections 6.3.3.1 loss of communication interface if a spi communication error occurs, then the device is switched into fail mode. an spi communication fault is detected if: ? the wd bit is not toggled with each spi message, or ? wd timeout is reached, or ? protocol length erro r (modulo 16 check) the si stuck to static levels during csb period and v cc fail (spi not functional) are indirectly detected by wd toggle error. the spi communication error is reported in ? spi failure flag (spif) inside the device status register #7 in the next spi communication as long as the device is in fail mode, the spif bit retains its state. the spif bit is delatched during the tr ansition from fail-to-normal modes. 6.3.3.2 logic i/o plausibility check the logic and signal i/o are protected against fatal mistreatment by signal plausibility check according following table: the limp and the in1? in4 have an input symmetrically deglitch time t in_dgl = 200 s (typ). if the limp input is set to logic [1] for a delay longer than 200 s (typ), the device is switched into fail mode (internal signal called ilimp). figure 34. limp and ilimp signal in case the inx input is set to logic [1] for a delay longer than 200 s (typ.), the corresponding channel is controlled by the direct signal (internal signal called iinx). ? i/o signal check strategy in1 ~ in4 fre quency ab ove limi t (lo w pass filter) limp frequency above limit (low pass filter) rst\ frequency above limit (low pass filter) c lk fre quency ab ove limi t (lo w pass filter) limp time ilimp time t in_dgl 200s typ. t in_dgl 200s typ. analog integrated circuit device data ? freescale semiconductor 57 mc17XSF500 figure 35. in, iin, and in_on signal the rstb has an input deglitch time t rst_dgl = 10 s (typ) for the falling edge only. the clk has an input symmetrically deglitch time t clk_dgl = 2.0 s (typ). due to the input deglit cher (at the clk input) a very high input frequency leads to a clock fail detection. the clk fail detection (clock input frequency detection f clk low ) is started immediately with the positive edge of the rstb signal. if the clk frequency is below f clk low limit, the output st ate will depend on the corresponding chx signal. as soon as the clk signal is va lid, the output duty cycle depends on the corresp onding spi configuration. to delatch the clk fail diagnosis: ? the clock failure condition must be removed ? a read command of the quick stat us register #1 must be performed 6.3.3.3 electrical characterization table 20. electrical characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes logic i/o limp in1? in4 clk t wd spi watchdog timeout ? wd sel = 0 ? wd sel = 1 24 96 32 128 40 160 ms t toggle input toggle time for in1? in4 768 1024 1280 ms t dgl input deglitching time ? limp and in1? in4 ?clk ?rst\ 150 1.5 7.5 200 2.0 10 250 2.5 12.5 s f clock low clock low frequency detection 50 100 200 hz inx time iinx time inx_on time t toggle t in_dgl t toggle 1024ms typ. t in_dgl 200s typ. t in_dgl t in_dgl t in_dgl t in_dgl analog integrated circuit device data ? 58 freescale semiconductor mc17XSF500 6.3.4 external smart power control (out6) the device provides a control outpu t to drive an external smart power device in normal mode only. the control is according to the channel 6 settings in the spi input data register. ? the protection and current feedback of the external smartmos device are under t he responsibility of the microcontroller. ? the output delivers a 5.0 v cmos logic signal from v cc . the output is protecte d against overvoltage. an external current limit resistor (i.e. 1.0 k ? ...10 k ? ) shall be used to handle negative output voltage conditions. the output has an integrated pull-down resistor to provid e a stable off condition in sleep mode and fail mode. in case of a ground disconnection, the out6 voltage is pulled up. external components are man datory to define the state of external smart power device, and to limit possible reverse out6 current (i.e. resistor in series). 6.3.4.1 electrical characterization table 21. electrical characteristics characteristics noted under conditions 7.0 v ? v pwr ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes external smart power output out6 t out6 rise out6 rising edge for 100 pf capacitive load ?? 5.0s r out6 dwn out6 pull-down resistor 5.0 10 20 k ? v oh logic output high state level (out6) v cc - 0.6 ? ? v v ol logic output low state level (out6) ?? 0.6v analog integrated circuit device data ? freescale semiconductor 59 mc17XSF500 7 typical applications 7.1 introduction the 17XSF500 is the latest achievement in drivers for all types of centraliz ed lighting applications. 7.1.1 application diagram figure 36. typical front lighting application for automotive si cp vcc vbat csb out1 in4 gnd sclk so out2 rstb clk out3 csns syncb out4 limp in1 out5 in2 in3 out6 so vcc a/d3 gnd csb sclk si main mcu rstb clk a/d1 limp vbat in4 gnd in1 in2 watchdog in3 vbat vcc gnd 5v regulator 1k in out vbat csns gnd smart power 5k trig1 a/d2 spare 10n parking light 10n flasher 10n low beam 10n fog light 10n high beam 10n 100n 10n?100n 5k 1k 1k 10 100n 1k 1k 1k 1k 1k si cp vcc vbat csb out1 in4 gnd sclk so out2 rstb clk out3 csns syncb out4 limp in1 out5 in2 in3 out6 1k in out vbat csns gnd smart power spare 10n parking light flasher low beam fog light high beam 100n 10n?100n 100n vpwr right vpwr left 1k 10n 10n 10n 10n 10n 20v 20v 10n vcc gnd vcc clamp 10k vpwr vpwr vpwr vpwr analog integrated circuit device data ? 60 freescale semiconductor mc17XSF500 7.1.2 application instructions 7.1.3 bill of material table 22. 17XSF500 bill of material (26) signal location mission value v pwr close to gen4 extreme switch reduction of emission and immunity 100 nf (x7r 50 v) cp close to gen4 extreme switch charge pump tank capacitor 100 nf (x7r 50 v) v cc close to gen4 extreme switch reduction of emission and immunity 10 nf to 100 nf (x7r 16 v) out1? out5 close to output connector sustain esg gun and fast transient pulses 10 nf to 22 nf (x7r 50 v) csns close to mcu output current sensing 5.0 k ( ? 1.0%) csns close to mcu low pass filter removing noise 10 k ? ( ? 1.0%) & 10 nf (x7r 16 v) csns syncb n/a pull up resistor for the sy nchronization of a/d conversion 5.0 k ( ? 1.0%) in1? in4 n/a sustain high-voltage 1.0 k ? ( ? 1.0%) out6 n/a sustain reverse supply 1.0 k ? ( ? 1.0%) to increase fast transi ent pulses robustness v pwr close to connector sustain pulse #1 in case of led loads or without loads 20 v zener diode and diode in series per supply line v pwr close to gen4 extreme switch sustain pulse #2 without loads additional 10 f (x7r 50 v) to sustain 5.0 v voltage regulator failure mode v cc close to 5.0 v voltage regulator prevent high-voltage application on the mcu 5.0 v zener diode and a bipolar transistor notes 26. freescale does not assume liability, endorse, or warrant compon ents from external manufacturers that are referenced in circu it drawings or tables. while freescale offers component recommendations in this configuration, it is the cust omer?s responsibility to valid ate their application. analog integrated circuit device data ? freescale semiconductor 61 mc17XSF500 7.2 emc & emi considerations 7.2.1 emc/emi tests this paragraph gives emc/emi performance, according to auto motive specifications. further generic design recommendations can be e.g. found on the freescale web site www.freescale.com. 7.2.2 fast transient pulse tests this paragraph gives the device perform ances against fast transient disturbances. table 23. 17XSF500 emc/emi performances test signals conditions automotive standard criteria conducted emission vpwr outputs off outputs on in pwm cispr25 class 5 150 ? method global pins: v pwr and out1? out5 local pins: v cc , cp, and csns iec 61967-4 150 ? method global pins: 12-l level (27) local pins: 10-k level conducted immunity global pins: v pwr and out1? out5 local pins: v cc iec 62132-4 class a related to the outputs state and the analog diagnostics ( ? 20%) 30 dbm for global pins 12 dbm for local pins notes 27. with additional 2.2 nf decoupling capacitor on vpwr table 24. 17XSF500 fast transient capability on vpwr test conditions automotive standard criteria pulse 1 outputs loaded with lamps other cases with external transient voltage suppressor iso 7637-2 class a pulse 2a pulse 3a / 3b outputs loaded outputs unloaded pulse 5b (40 v) analog integrated circuit device data ? 62 freescale semiconductor mc17XSF500 7.3 robustness considerations the short-circuit protections embedded in 17XSF500 are preferred to conventional current limitations, to minimize the thermal overstress within the device in case of an overload condition. the junction temperature elevation is drastically reduced to a v alue which does not affect the device?s reliabili ty. moreover, the availability of the lighting is guaranteed in fail mode by the un limited auto-restart feature. chapter 12 of aec-q100 specification published by the automotive electronics council, presents a turn-on into short-circuit condition. it is not enough because the short-circuit even t can also occur in on-state. the 17XSF500 test plan at t a = 70 c is presented in table 25 . the tests were performed on 30 parts fr om 3 engineering lots (total 90 pieces). for either conditions, contact our local field application engineer (email: support@freescale.com). table 25. 17XSF500 repetitive short-circuit test results at t a = 70 c short-circuit case supply voltage supply line load line cycles without failure turn-on into short-circuit condition 16 v 0.3 m /2.5 mm2 5.0 m /1.0 mm2 500 k 0.3 m / 1.0 mm2 500 k 5.0 m /2.5 mm2 500 k short-circuit in on-state (28) 14 v 0.3 m /2.5 mm2 5.0 m /1.0 mm2 500 k 0.3 m / 1.0 mm2 500 k 5.0 m /2.5 mm2 500 k notes 28. the channel was loaded in the on-state with 100 ma. table 26. 17XSF500 aecq100-12 reliability test results at t a = 85 c and supply voltage = 14 v short-circuit case supply line load line aecq100-12 grade load short-circuit 5.0 ? h/10 m ? 5.0 ? h/50 m ? d analog integrated circuit device data ? freescale semiconductor 63 mc17XSF500 7.4 pcb layout recommendations this new generation of high-side switch prod ucts family facilitates ecu design thanks to compatible mcu software and pcb foot print for each device variant. the pcb copper layer is similar fo r all devices in the family, only the solder stencil opening i s different. figure 37. pcb copper layer & solder stencil opening recommendations analog integrated circuit device data ? 64 freescale semiconductor mc17XSF500 7.5 thermal information this section is to provide thermal information. 7.5.1 thermal transient figure 38. transient thermal response curve 7.5.2 r/c thermal model contact our local field application engineer (email: support@freescale.com). analog integrated circuit device data ? freescale semiconductor 65 mc17XSF500 8 packaging 8.1 marking information device markings indicate information on the week and year of manu facturing. the date is coded wit h the last four characters of the nine character build information code (e.g. ?ctkah1229?). the date is coded as four numerical digits where the first two di gits indicate the year and the last two digits indicate the week. for instance, the date code ?1229? indicates the 29 th week of the year 2012. 8.2 package mechanical dimensions package dimensions are provided in package drawings. to find the most current package outline drawing, go to www.freescale.com and perform a keyword sear ch for the drawing?s document number. table 27. package outline package suffix package outline drawing number 32-pin soicw-ep ek 98asa00368d analog integrated circuit device data ? 66 freescale semiconductor mc17XSF500 ek suffix 32-pin soic-ep 98asa00368d issue 0 analog integrated circuit device data ? freescale semiconductor 67 mc17XSF500 ek suffix 32-pin soic-ep 98asa00368d issue 0 analog integrated circuit device data ? 68 freescale semiconductor mc17XSF500 ek suffix 32-pin soic-ep 98asa00368d analog integrated circuit device data ? freescale semiconductor 69 mc17XSF500 9 revision history revision date description of changes 1.0 9/2013 ? initial release 2.0 9/2013 ? added the note ?to achieve high re liability over 10 years of c ontinuous operation, the device's continuous operating junction te mperature should not exceed 125 ? ? c.? to operating temperature ? corrected one typo error for power channel current document number: mc17XSF500 rev. 2.0 9/2013 information in this document is provi ded solely to enable system and software implementers to use freescale products. there are no express or implied copyri ght licenses granted hereunder to design or fabricate any inte grated circuits based on the information in this document. freescale reserves the right to make changes without fu rther notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitabilit y of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or spec ifications can and do vary in differ ent applications, and actual performance may vary over time. all operating parameters, including ?typic als,? must be validated for ea ch customer application by customer?s technical experts. freescale does not convey an y license under its patent rights nor the rights of others. freescale sells products pursuant to standar d terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions . freescale and the freescale logo, are trademarks of free scale semiconductor, inc., re g. u.s. pat. & tm. off. smartmos is a trademark of freescale semiconductor, inc. a ll other product or service name s are the property of their respective owners. ? 2013 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support |
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